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datasheet high-performance 6-channel ac?97 2.3 codec with universal jacks? stac9758/9759 idt? 1 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? overview high performance, 6-channel, ac?97 2.3 codecs with high signal-to-noise ratio and low distortion. features ? high performance sd technology ? 6-channel ac?97 2.3 codecs ? 20-bit full duplex stereo adcs ? 20-bit full duplex dacs ? headphone drive capability ? spdif_in support ? spdif_out support, including 96 khz ? adat ? optical ?litepipe? interface support ? universal jacks tm functionality for jack interchangeability ? internal jack sensing ? crystal elimination circuit ? front/rear stereo microphone ? 96 khz dac playback support ? up to 5 general purpose i/os ? digital and analog pc beep ? ac?97 2.3 paging registers and analog plug and play capability ? energy saving dynamic power modes ? >90 db snr and >-90dbv thd+n ? adjustable vref_out control ? pin compatible with 2-channel codecs ? independent sample rates for adc & dacs ? +3.3 v & +5 v analog power supply options description idt's stac9758/9759 are general purpose 20-bit, full duplex, 6-channel audio codecs conforming to the ana- log component specification of ac '97 (audio codec 97 component specification rev. 2.3 ). the stac9758/9759 incorporates idt's proprietary sd technology to achieve a dac snr in excess of 90db. with idt?s headphone drive capability, headphones can be driven without an external amplifier. the stac9758/9759 communicates via the five ac-link to any digital component of ac '97, providing flexi- bility in the audio system design. packaged in an ac '97 compliant 48-pin tqfp, the stac9758/9759 can be placed on the motherboard, daughter boards, pci, amr, cnr, mdc or acr cards. supported adc and dac audio sample rates include 96khz, 48khz, 44.1khz, 32khz, 22.05khz, 16khz, 11.025khz, and 8khz; additional rates are supported in the stac9758/9759 soft audio drivers . all adcs and dacs operate at 20-bit resolution. spdif_out supported sample rates include 96khz, 48khz, 44.1khz and 32khz. spdif_in supports 48khz and 44.1khz. the stac9758/9759 includes internal jack sensing using proprietary idt current and impedance-sensing tech- niques. the impedance load on any of the inputs or outputs can be detected. the stac9758/9759 also supports uni- versal jacks tm functionality for jack interchangeability. the gpios on the stac9758/9759 remain available for advanced configurations. the stac9758/9759 can sup- port up to 5 gpios. the stac9758/9759 is designed primarily to support 6-channel audio. additionally, the stac9758/9759 pro- vides for a stereo enhancement feature, idt surround 3d (ss3d). the stac9758/9759 also supports the adat ? optical ?litepipe? interface, which provides an 8 channel output for professional and consumer audio applications. the stac9758/9759 can be soundblaster ? and windows sound system ? compatible when used with idt?s wdm driver for windows 98/2k/me/xp or with intel/microsoft driver included with windows 2k/me/xp. soundblaster is a registered trademark of creative labs. windows is a registered trademark of microsoft corporation. adat optical is a registered trademark of alesis corporation.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 2 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? table of contents 1. description ........................................................................................................................... 7 1.1. features ................................................................................................................................ ........... 8 1.2. block diagram ................................................................................................................................ ... 9 2. characteristics/specifications ................................................................................ 10 2.1. electrical specifications ................................................................................................................... 10 2.1.1. absolute maximum ratings ............................................................................................... 10 2.1.2. recommended operation conditions ............................................................................... 10 2.1.3. power consumption ......................................................................................................... 11 2.1.4. ac-link static digital specifications ................................................................................. 12 2.1.5. stac9758 5v analog performance characteristics ........................................................ 12 2.1.6. stac9759 3.3v analog performance characteristics ..................................................... 14 2.2. ac timing characteristics ............................................................................................................... 17 2.2.1. cold reset ......................................................................................................................... 17 2.2.2. warm reset ....................................................................................................................... 17 2.2.3. clocks ................................................................................................................................ 18 2.2.4. stac9758/9759 crystal elimination circuit and clock frequencies ................................ 19 2.2.5. data setup and hold ........................................................................................................ 20 2.2.6. signal rise and fall times ................................................................................................ 20 2.2.7. ac-link low power mode timing ..................................................................................... 21 2.2.8. ate test mode .................................................................................................................. 21 3. typical connection diagram ....................................................................................... 22 3.1. split independent power supply operation .................................................................................... 23 4. controller, codec and ac-link ................................................................................. 25 4.1. ac-link physical interface ............................................................................................................... 25 4.2. controller to single codec ............................................................................................................ 25 4.3. controller to multiple codecs ........................................................................................................ 27 4.3.1. primary codec addressing ............................................................................................. 27 4.3.2. secondary codec addressing ........................................................................................ 27 4.3.3. codec id strapping ......................................................................................................... 28 4.4. clocking for multiple codec implementations ............................................................................... 28 4.5. stac9758/9759 as a primary codec ........................................................................................... 28 4.5.1. stac9758/9759 as a secondary codec ........................................................................ 28 4.6. ac-link power management ........................................................................................................... 29 4.6.1. powering down the ac-link .............................................................................................. 29 4.6.2. waking up the ac-link ...................................................................................................... 29 4.6.3. codec reset ................................................................................................................... 30 5. ac-link digital interface .............................................................................................. 31 5.1. overview ................................................................................................................................ ......... 31 5.2. ac-link serial interface protocol .................................................................................................... 32 5.2.1. ac-link variable sample rate operation ......................................................................... 33 5.2.2. variable sample rate signaling protocol .......................................................................... 33 5.2.3. primary and secondary codec register addressing ...................................................... 34 5.3. ac-link output frame (sdata_out) ............................................................................................ 35 5.3.1. slot 0: tag / codec id ................................................................................................... 36 5.3.2. slot 1: command address port ......................................................................................... 36 5.3.3. slot 2: command data port ............................................................................................... 37 5.3.4. slot 3: pcm playback left channel .................................................................................. 37 5.3.5. slot 4: pcm playback right channel ................................................................................ 37 5.3.6. slot 5: modem line 1 output channel .............................................................................. 37 5.3.7. slot 6 - 11: dac ................................................................................................................. 37 5.3.8. slot 12: audio gpio control channel ............................................................................... 38 5.4. ac-link input frame (sdata_in) ................................................................................................. 38 5.4.1. slot 0: tag ........................................................................................................................ 39
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 3 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.4.2. slot 2: status data port ..................................................................................................... 40 5.4.3. slot 3: pcm record left channel ..................................................................................... 41 5.4.4. slot 4: pcm record right channel ................................................................................... 41 5.4.5. slot 5: modem line 1 adc ................................................................................................ 41 5.4.6. slot 6-9: adc ..................................................................................................................... 41 5.4.7. slots 7-8: vendor reserved .............................................................................................. 41 5.4.8. slot 10 & 11: adc ............................................................................................................. 41 5.4.9. slot 12: reserved .............................................................................................................. 41 5.5. ac-link interoperability requirements and recommendations ...................................................... 42 5.5.1. ?atomic slot? treatment of slot 1 address and slot 2 data ............................................... 42 5.6. slot assignments for audio ............................................................................................................. 42 6. stac9758/9759 mixer ......................................................................................................... 45 6.1. spdif digital mux ........................................................................................................................... 45 6.2. spdif_in ......................................................................................................................... 45 6.3. adat optical ?lightpipe? support ................................................................................................... 46 6.4. digital pc beep ............................................................................................................................... 46 6.5. double rate audio .......................................................................................................................... 46 6.6. double rate spdif output ............................................................................................................. 46 7. stac9758/9759 mixer diagram ........................................................................................ 47 8. programming registers ................................................................................................ 48 8.1. program register list ...................................................................................................................... 48 8.2. program register descriptions ........................................................................................................ 50 8.2.1. reset (00h) ........................................................................................................................ 50 8.2.2. master volume registers (02h) ......................................................................................... 51 8.2.3. dac-a volume register (04h) .......................................................................................... 52 8.2.4. master volume mono (06h) ............................................................................................. 53 8.2.5. pc beep volume (0ah) .................................................................................................... 53 8.2.6. digital pc beep ................................................................................................................. 54 8.2.7. phone volume (0ch) ......................................................................................................... 54 8.2.8. mono/stereo mic volume (0eh) ........................................................................................ 56 8.2.9. line in volume (10h) ......................................................................................................... 58 8.2.10. cd volume (12h) ............................................................................................................. 59 8.2.11. dac-b to mixer2 volume control (14h) ........................................................................... 60 8.2.12. aux volume (16h) ............................................................................................................ 62 8.2.13. pcmout volume (18h) .................................................................................................... 63 8.2.14. record select (1ah) ........................................................................................................ 64 8.2.15. record gain (1ch) .......................................................................................................... 65 8.2.16. general purpose (20h) .................................................................................................... 66 8.2.17. 3d control (22h) .............................................................................................................. 67 8.2.18. audio interrupt and paging (24h) .................................................................................... 68 8.2.19. powerdown ctrl/stat (26h) .............................................................................................. 70 8.2.20. extended audio id (28h) ................................................................................................. 72 8.2.21. extended audio control/status (2ah) .............................................................................. 74 8.3. pcm dac rate registers ............................................................................................................... 76 8.3.1. pcm dac rate (2ch) ....................................................................................................... 77 8.3.2. pcm surround dac rate (2eh) ........................................................................................ 77 8.3.3. pcm lfe dac rate (30h) ................................................................................................ 77 8.3.4. pcm lr adc rate (32h) .................................................................................................. 78 8.3.5. center/lfe volume (36h) .................................................................................................. 78 8.3.6. surround volume (38h) ..................................................................................................... 78 8.3.7. spdif control (3ah) .......................................................................................................... 79 8.4. general purpose input & outputs ................................................................................................... 81 8.4.1. eapd ................................................................................................................................ . 81 8.4.2. gpio pin definitions .......................................................................................................... 81 8.4.3. gpio pin implementation .................................................................................................. 81
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 4 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.4.4. extended modem status and control register (3eh) ........................................................ 82 8.4.5. gpio pin configuration register (4ch) ............................................................................. 82 8.4.6. gpio pin polarity/type register (4eh) ............................................................................. 83 8.4.7. gpio pin sticky register (50h) ......................................................................................... 83 8.4.8. gpio pin mask register (52h) .......................................................................................... 84 8.4.9. gpio pin status register (54h) ........................................................................................ 84 8.5. extended codec registers page structure definition .................................................................. 85 8.5.1. extended registers page 00 ............................................................................................. 85 8.5.2. extended registers page 01 ............................................................................................. 85 8.5.3. extended registers page 02, 03 ....................................................................................... 85 8.6. stac9758/9759 paging registers ................................................................................................. 85 8.6.1. spdif_in status 1 register (60h, page 00h ) ..................................................................... 86 8.6.2. codec class/rev (60h page 01h ) .................................................................................... 86 8.6.3. spdif_in status 2 register (62h, page 00h ) ..................................................................... 87 8.6.4. pci svid (62h page 01h ) ................................................................................................... 88 8.6.5. universal jack tm output select (64h, page 00h ) ............................................................... 88 8.6.6. pci ssid (64h page 01h ) ................................................................................................... 89 8.6.7. universal jack tm input select (66h, page 00h ) .................................................................. 90 8.6.8. function select (66h page 01h ) .......................................................................................... 91 8.6.9. i/o misc. (68h, page 00h ) ................................................................................................... 92 8.6.10. function information (68h page 01h ) ................................................................................ 93 8.6.11. digital audio control (6ah, page 00h ) .............................................................................. 95 8.6.12. sense details (6ah page 01h ) .......................................................................................... 96 8.6.13. revision code (6ch, page 00h ) ........................................................................................ 97 8.6.14. dac slot mapping (6ch, page 01h ) ................................................................................. 97 8.6.15. analog special (6eh, page 00h ) ....................................................................................... 98 8.6.16. adc slot mapping (6eh, page 01h ) ................................................................................ 100 8.6.17. idt reserved (70h) ....................................................................................................... 100 8.6.18. various functions (72h) ................................................................................................ 100 8.6.19. eapd access register (74h) ........................................................................................ 102 8.6.20. analog misc. (76h) ......................................................................................................... 103 8.6.21. adat control and hpf bypass (78h) ........................................................................... 103 8.6.22. idt reserved register (7ah) ........................................................................................ 103 8.7. vendor id1 and id2 (7ch and 7eh) .............................................................................................. 104 8.7.1. vendor id1 (7ch) ............................................................................................................ 104 8.7.2. vendor id2 (7eh) ............................................................................................................. 104 9. low power modes .......................................................................................................... 105 10. multiple codec support ........................................................................................... 107 10.1. primary/secondary codec selection ........................................................................................ 107 10.1.1. primary codec operation ........................................................................................... 107 10.1.2. secondary codec operation ....................................................................................... 107 10.2. secondary codec register access definitions ......................................................................... 108 11. testability ...................................................................................................................... 109 11.1. ate test mode ........................................................................................................................... 109 12. pin description .............................................................................................................. 110 12.1. digital i/o ................................................................................................................................ ..... 110 12.2. analog i/o ................................................................................................................................ ... 111 12.3. filter/references ......................................................................................................................... 112 12.4. power and ground signals ......................................................................................................... 112 13. ordering information ................................................................................................ 113 14. package drawing ......................................................................................................... 113 15. 48-pin lqfp solder reflow profile ....................................................................... 114 15.1. standard reflow profile data ...................................................................................................... 114 15.2. pb free process - package classification reflow temperatures ............................................... 115
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 5 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 16. appendix a: programming registers ................................................................... 116 17. revision history ........................................................................................................... 118 list of figures figure 1. cold reset timing .......................................................................................................................... 17 figure 2. warm reset timing ........................................................................................................................ 17 figure 3. clocks timing ................................................................................................................................ . 18 figure 4. data setup and hold timing .......................................................................................................... 20 figure 5. signal rise and fall times timing ................................................................................................. 20 figure 6. ac-link low power mode timing .................................................................................................. 21 figure 7. ate test mode timing ................................................................................................................... 21 figure 8. typical connection diagram .......................................................................................................... 22 figure 9. split independent power supply operation ................................................................................... 24 figure 10. ac-link to its companion controller ............................................................................................ 25 figure 11. codec clock source detection .................................................................................................. 26 figure 12. stac9758/9759 powerdown timing ........................................................................................... 29 figure 13. bi-directional ac-link frame with slot assignments .................................................................. 31 figure 14. ac-link audio output frame ....................................................................................................... 35 figure 15. start of an audio output frame ................................................................................................... 35 figure 16. stac9758/9759 audio input frame ........................................................................................... 38 figure 17. start of an audio input frame ...................................................................................................... 38 figure 18. bi-directional ac-link frame with slot assignments ................................................................... 43 figure 19. stac9758/9759 mixer diagram .................................................................................................. 47 figure 20. example of stac9758/9759 powerdown/powerup flow .......................................................... 105 figure 21. powerdown/powerup flow with analog still active .................................................................. 106 figure 22. pin description drawing ............................................................................................................. 110 figure 23. solder reflow profile ................................................................................................................. 114
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 6 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? list of tables table 1. clock mode configuration ............................................................................................................... 19 table 2. common clocks and sources ......................................................................................................... 19 table 3. recommended codec id strapping .............................................................................................. 28 table 4. ac-link output slots (transmitted from the controller) .................................................................. 31 table 5. the ac-link input slots (transmitted from the codec) ................................................................ 32 table 6. vra behavior ................................................................................................................................ .. 33 table 7. output slot 0 bit definitions ............................................................................................................. 36 table 8. command address port bit assignments ........................................................................................ 37 table 9. input slot 1 bit definitions ............................................................................................................... 39 table 10. status address port bit assignments ............................................................................................ 40 table 11. status data port bit assignments .................................................................................................. 40 table 12. primary codec addressing: slot 0 tag bits ................................................................................ 42 table 13. secondary codec addressing: slot 0 tag bits ........................................................................... 42 table 14. ac-link slot definitions ................................................................................................................. 43 table 15. ac-link input slots dedicated to audio ....................................................................................... 43 table 16. audio interrupt slot definitions ...................................................................................................... 44 table 17. programming registers ................................................................................................................. 48 table 18. digital pc beep examples ............................................................................................................. 54 table 19. amap compliant ........................................................................................................................... 76 table 20. hardware supported sample rates .............................................................................................. 77 table 21. gain or attenuation examples ....................................................................................................... 94 table 22. sensed bits ................................................................................................................................ ... 96 table 23. low power modes ....................................................................................................................... 105 table 24. codec id selection ................................................................................................................... 107 table 25. secondary codec register access slot 0 bit definitions ......................................................... 108 table 26. test mode activation ................................................................................................................... 109 table 27. ate test mode operation ........................................................................................................... 109 table 28. digital connection signals ........................................................................................................... 110 table 29. analog connection signals ......................................................................................................... 111 table 30. filtering and voltage references ................................................................................................ 112 table 31. power and ground signals .......................................................................................................... 112
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 7 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 1. description idt's stac9758/9759 are general purpose 20-bit, full duplex, 6-channel audio codecs conform- ing to the analog component specification of ac '97 (audio codec 97 component specification rev. 2.3 ). the stac9758/9759 incorporates idt's proprietary sd technology to achieve a dac snr in excess of 90db. with idt?s headphone drive capability, headphones can be driven without an exter- nal amplifier. the stac9758/9759 communicates via the five ac-link to any digital component of ac '97, providing flexibility in the audio system design. packaged in an ac '97 compliant 48-pin tqfp, the stac9758/9759 can be placed on the motherboard, daughter boards, pci, amr, cnr, mdc or acr cards. supported adc and dac audio sample rates include 96khz, 48khz, 44.1khz, 32khz, 22.05khz, 16khz, 11.025khz, and 8khz; additional rates are supported in the stac9758/9759 soft audio drivers . all adcs and dacs operate at 20-bit resolution. spdif_out supported sample rates include 96khz, 48khz, 44.1khz and 32khz. spdif_in supports 48khz and 44.1khz. the stac9758/9759 includes internal jack sensing using proprietary idt current and imped- ance-sensing techniques. the impedance load on any of the inputs or outputs can be detected. the stac9758/9759 also supports universal jacks tm functionality for jack interchangeability. the gpios on the stac9758/9759 remain available for advanced configurations. the stac9758/ 9759 can support up to 5 gpios. the stac9758/9759 implementation of internal jack sense uses the extended paging registers defined by the ac'97 2.3 specification. this allows for additional registry space to hold the identifi- cation information about the codec, the jack sensing details and results, and the external sur- roundings of the codec. the information within the extended paging registers will allow for the automatic configuration of the audio subsystem without end-user intervention. for example, the bios can populate the extended paging registers with valuable information for both the audio driver and the operating system such as gain and attenuation stages, input population and input phase and jack location. with this input information, the idt driver will automatically provide to the volume control panel only the volume sliders that are implemented in the system, thus improving the end-user's experience with the pc. the information in the extended paging registers will also allow for automatic configuration of microphone inputs, the ability to switch between spdif and analog outputs, the routing of the mas- ter volume slider to the proper physical output, and softeq configurations. the fully parametric idt softeq can be initiated upon jack insertion and removal. the stac9758/9759 is designed primarily to support 6-channel audio. additionally, the stac9758/ 9759 provides for a stereo enhancement feature, idt surround 3d (ss3d). the stac9758/9759 also supports the adat ? optical ?litepipe? interface, which pro- vides an 8 channel output for professional and consumer audio applications. the stac9758/9759 can be soundblaster ? and windows sound system ? compatible when used with idt?s wdm driver for windows 98/2k/me/xp or with intel/microsoft driver included with windows 2k/me/xp. soundblaster is a registered trademark of creative labs. windows is a registered trademark of microsoft corporation. adat optical is a registered trademark of alesis corporation.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 8 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 1.1. features ? six channel, ac?97 revision 2.3 compliant ? 20-bit adcs ? 20-bit dacs ? 96khz sample rate support ? spdif output at 32khz, 44.1khz, and 48khz ? double rate spdif output at 96khz ? adat optical lightpipe output ? 8 channel, 20 bit output at 48khz and 44.1khz ? spdif input at 48khz and 44.1khz with internal jack sensing ? headphone amplifier with 50mw per channel ? programmable +3db voltage gain ? universal jacks tm and 3-jack/6-channel jack-sharing ? the stac9758/9759 supports 5 stereo analog i/o ports. ? these ports correspond to the following ac?97 referenced pins: mic1/2 (21/22), line_in (23/ 24), line_out (35/36), surround (39/41), center/lfe (43/44). ? these 5 ports may be used in the common ?jack sharing? implementation or in a completely reconfigurable (universal jacks tm ) configuration. ? pins 35 and 36 = headphone (default) ? pins 23 and 24 = line_in (default) or surround out. ? pin 21 and 22 = microphone (default, mono) or ctr/lfe out. ? rear jacks are dynamically reconfigurable to input or output. ? internal jack sense is used to detect attached devices and inform the driver to reconfigure the jack as appropriate. ? all ?universal jacks tm ? pins (as well as pins 16/17) may also be inputs. ? mixer inputs ? analog pc beep, digital pc beep, phone, aux in, line in (has pre-select mux for jack sharing/ universal jacks tm ), mic in (mono and stereo modes - includes pre-select mux), dac-a, dac-b ? split-mute option on all stereo inputs allows left and right inputs to be muted independently. ? analog output sources ? dac-a, dac-b, dac-c, stereo mix, mono ? analog i/o ? pins 21/22, 23/24, 35/36, 39/41, 43/44 ? all analog i/o pins have analog jack sense ? pins 35/36 and 39/41 are capable of driving headphones ? all outputs are high impedance when powered down ? split-mute (bit d7) option on all outputs allows left and right outputs to be muted independently ? internal microphone sensing ? mono and dual stereo microphone support ? adjustable vrefout control ? extended ac?97 2.3 paging registers
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 9 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? ? up to 5 gpio depending upon configuration ? power management ? idt ss3d ? primary and secondary mode operation ? high performance sigma-delta technology ? digital and analog pc beep option ? digital-ready status ? crystal elimination circuit ? 0, 10db, 20db, and 30 db microphone boost capability ? +3.3 v (stac9759) and +5 v (stac9758) analog power supply options 1.2. block diagram hp_out ac-link digital interface sync bit_clk sdata_out sdata_in reset# power management dac-a pair dac-b pair adc adc pcm out dacs pcm in adcs mono_out mic boost 0,10, 20 or 30 db left or right channel stereo or mono mic mixer analog mixing and gain control line_out multi-codec cid0 cid1 spdif output variable sample rate 20-bit dacs and 20-bit adcs dac-c pair adat lightpipe spdif input m u x m u x left or right channel stereo or mono mic universal jacks tm jack sharing internal jack sense line in digital pcbeep mic sensing pc_beep phone cd aux
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 10 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2. c haracteristics/specification s 2.1. e lectrical specifications 2.1.1. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the stac9758/9759. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. 2.1.2. recommended operation conditions item pin maximum rating analog maximum supply voltage avdd 6 volts digital maximum supply voltage dvdd 5.5 volts v refout output current 5 ma voltage on any pin relative to ground vss - 0.3 v to vdd + 0.3 v operating temperature 0 o c to +70 o c storage temperature -55 o c to +125 o c soldering temperature 260 o c for 10 seconds * soldering temperature information for all available packages begins on page 114 . parameter min. typ. max. units power supply voltage digital - 3.3 v 3.135 3.3 3.465 v analog - 5 v 4.75 5 5.25 v analog - 3.3 v 3.135 3.3 3.465 v ambient operating temperature 0 +70 c case temperature t case (48-lqfp) +90 c esd: the stac9758/9759 is an esd (electrostatic discharge) sensitive device. the human body and test equipment can accumulate and discharge electrostatic charges up to 4000 volts without detection. even though the stac9758/9759 implements internal esd protection circuitry, proper esd precautions should be followed to avoid damaging the functionality or performance.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 11 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2.1.3. power consumption parameter min typ max unit digital supply current + 3.3 v digital - 44 - ma analog supply current (at reset state) + 5 v analog - 58 - ma + 3.3 v analog - 52 - ma power down status (individually asserted) (all pr measurements taken while unmuted.) all paths unmuted +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 96 88 49 - ma pr0 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 90 82 39 - ma pr1 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 71 66 34 - ma pr2 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 51 45 22 - ma pr3 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 28 26 22 - ma pr4 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 104 89 1.3 - ma pr5 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 89 83 22 - ma pr6 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 84 79 49 - ma pr0 & pr1 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 65 61 22 - ma pr0, pr1, pr2, pr6 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 12 11 22 - ma pr0, pr1, pr2, pr3, pr6 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 0.8 0.6 22 - ma pr0, pr1, pr2, pr3, pr4, pr6 +5v analog supply current +3.3v analog supply current +3.3v digital supply current - 0.8 0.6 1.3 - ma for additional power configuration, each dac pairs can be powered down individually.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 12 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2.1.4. ac-link static digital specifications (t ambient = 25 oc, dvdd = 3.3v 5%, avss=dvss = 0v) note: * due to an internal pull-down resistor, the bit_clk pin will exhibit less than 100 m a of leakage current when the codec is configured as primary. this pin meets the +/- 10 m a leakage specification when configured as secondary. 2.1.5. stac9758 5v analog performance characteristics (t ambient = 25 oc, avdd = 5.0v 5%, dvdd = 3.3v 5%, avss = dvss = 0v; 1 khz input sine wave; sample frequency = 48 khz; 0db = 1 vrms, 10k w/ 50pf load, testbench characterization bw: 20hz ? 20khz, 0db settings on all gain stages) parameter symbol min typ max unit input voltage range vin -0.30 - dvdd + 0.30 v low level input range vil - - 0.35 x dvdd v high level input voltage vih 0.65 x dvdd - - v high level output voltage voh 0.90 x dvdd - - v low level output voltage vol - - 0.1 x dvdd v input leakage current (ac-link inputs) - -10 - 10 m a output leakage current (high-impedance ac-link outputs) - -10 - 10 m a bit_clk (primary mode) output leakage current - -10 - 100* m a bit_clk (secondary mode) output leakage current - -10 - 10 m a output buffer drive current - - 8 ma bit_clk/spdif output drive current - - 24 ma parameter min typ max unit full scale input voltage: all analog inputs except mic - 1.00 - vrms microphone inputs (note 1) - 0.03 - vrms full scale output: line output - 1.00 - vrms pcm (dac) to line_out - 1.00 - vrms mono_out - 1.00 - vrms headphone_out (32 w load) per channel (peak) - 50 - mw dynamic range: -60db signal level (note 2) cd to line_out - 98 - db line / aux / video t o line_out - 100 - db pcm (dac) t o line_out - 85 - db pcm (dac) in bypass mode to line_out - 88 - db line_in to a/d (1 vrms input referenced) - 90 - db line_in to headphone_out - 94 - db
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 13 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? analog frequency response (note 3 ) 10 - 30,000 hz total harmonic distortion + noise (-3db): (note 4 ) cd to line_out - -90 - db line / aux / video t o line_out - -90 - db pcm (dac) t o line_out (full scale) - -86 - db pcm (dac) in bypass mode to line_out - -89 - db line_in to a/d (-3dbv input level) - -81 - db headphone_out ( 3 2 w load ) - -80 - db headphone_out (10 k w load) - -85 - db snr (idle channel) (note 5 ) dac to line_out - 85 - db dac in bypass mode - 87 - db line / aux / video to line_out - 100 - db line_in to a/d with high pass filter enabled - 92 - db a/d & d/a digital filter pass band (note 6 ) 20 - 19,200 hz a/d & d/a digital filter transition band 19,200 - 28,800 hz a/d & d/a digital filter stop band 28,800 - - hz a/d & d/a digital filter stop band rejection (note 7 ) -100 - - db dac out-of-band rejection (note 8 ) -55 - - db group delay (48 khz sample rate) - - 1 ms power supply rejection ratio (1 khz) - -70 - db power supply rejection ratio (20 khz) - -40 - db any analog input to line_out crosstalk (10 khz signal frequency) - -70 - db any analog input to line_out crosstalk (1 khz signal frequency) - -90 - db spurious tone rejection - -100 - db attenuation, gain step size - 1.5 - db input impedance - 50 - k w input capacitance - 15 - pf vrefout - 0.5 x avdd - v vref - 0.45x avdd - v interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db gain drift - 100 - ppm/oc dac offset voltage - 10 20 mv deviation from linear phase - - 1 degrees parameter min typ max unit
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 14 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? note: 1. with +30 db boost on, 1.00 vrms with boost off. 2. ratio of full scale signal to noise output with -60db signal, measured ?a weighted? over a 20 hz to a 20 khz bandwidth. 3. 1db limits for line output & 0 db gain, at -20dbv 4. ratio of full scale signal to thd+n output with -3db signal, measured ?a weighted? over a 20 hz to a 20 khz bandwidth. 48 khz sample frequency 5. ratio of full scale signal to idle channel noise output is measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 6. peak-to-peak ripple over passband meets 0.25db limits, 48 khz sample frequency. 7. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 8. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 2.1.6. stac9759 3.3v analog performance characteristic s (t ambient = 25 oc, avdd = dvdd = 3.3v 5%, avss=dvss=0v; 1 khz input sine wave; sample fre- quency = 48 khz; 0db = 1 vrms, 10k w/ 50pf load, testbench characterization bw: 20hz ? 20khz, 0db settings on all gain stages) line_out/mono_out load resistance 10 - - k w line_out/mono_out load capacitance - - 50 pf headphone_out load resistance - 32 - w headphone_out load capacitance - - 100 pf mute attenuation - 96 - db pll lock time - 100 200 m sec pll 24.576mhz clock jitter - - 750 psec pll frequency multiplication tolerance - - 12.5 ppm pll bit clock jitter - - 750 psec parameter min typ max unit full scale input voltage: all analog inputs except mic - 1.00 - vrms microphone inputs (note 1) - 0.03 - vrms full scale output: line output - 0.5 - vrms pcm (dac) to line_out - 0.5 - vrms mono_out - 0.5 - vrms headphone_out (32 w load) per channel (peak) - 12.5 - mw dynamic range: -60db signal level (note 2) cd to line_out - 85 - db line / aux / video to line_out - 85 - db pcm (dac) to line_out - 82 - db pcm (dac) in bypass mode to line_out - 83 - db line_in to a/d - 85 - db parameter min typ max unit
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 15 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? line_in to headphone_out - 85 - db analog frequency response (note 3) 10 - 30,000 hz total harmonic distortion + noise (-3db): (note 4) cd to line_out - -90 - db line / aux / video to line_out - -92 - db pcm (dac) to line_out (full scale) - -81 - db pcm (dac) in bypass mode to line_out - -84 - db line_in to a/d(-3dbv input level) - -81 - db headphone_out (32 w load) - -80 - db headphone_out (10 k w load) - -90 - db snr (idle channel) (note 5) dac to line_out - 83 - db dac in bypass mode - 86 - db line / aux / video to line_out - 100 - db line_in to a/d with high pass filter enabled - 88 - db a/d & d/a digital filter pass band (note 6) 20 - 19,200 hz a/d & d/a digital filter transition band 19,200 - 28,800 hz a/d & d/a digital filter stop band 28,800 - - hz a/d & d/a digital filter stop band rejection (note 7) -100 - - db dac out-of-band rejection (note 8) -55 - - db group delay (48 khz sample rate) - - 1 ms power supply rejection ratio (1 khz) - -70 - db power supply rejection ratio (20 khz) - -40 - db any analog input to line_out crosstalk (10 khz signal frequency) - -70 - db any analog input to line_out crosstalk (1 khz signal frequency) - -90 - db spurious tone rejection - -100 - db attenuation, gain step size - 1.5 - db input impedance - 50 - k w input capacitance - 15 - pf vrefout - 0.5 x avdd - v vref - 0.41x avdd - v interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db gain drift - 100 - ppm/oc dac offset voltage - 10 20 mv parameter min typ max unit
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 16 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? note: 1. with +30 db boost on, 1.00 vrms with boost off. 2. ratio of full scale signal to noise output with -60db signal, measured ?a weighted? over a 20 hz to a 20 khz bandwidth. 3. 1db limits for line output & 0 db gain, at -20dbv 4. ratio of full scale signal to thd+n output with -3db signal, measured ?a weighted? over a 20 hz to a 20 khz bandwidth. 48 khz sample frequency 5. ratio of full scale signal to idle channel noise output is measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 6. peak-to-peak ripple over passband meets 0.25db limits, 48 khz sample frequency. 7. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 8. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. deviation from linear phase - - 1 deg. line_out/mono_out load resistance 10 - - k w line_out/mono_out load capacitance - - 50 pf headphone_out load resistance - 32 - w headphone_out load capacitance - - 100 pf mute attenuation - 96 - db pll lock time - 100 200 m sec pll 24.576mhz clock jitter - - 750 psec pll frequency multiplication tolerance - - 12.5 ppm parameter min typ max unit
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 17 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2.2. ac timing characteristics (t ambient = 25 c, avdd = 3.3v or 5v 5%, dvdd = 3.3v 5%, avss=dvss=0v; 50pf external load) 2.2.1. c old reset note: bit_clk and sdata_in are in a high impedance state during reset. 2.2.2. warm reset parameter symbol min typ max units reset# active low pulse width tres_low 1.0 - - m s reset# inactive to sdata_in or bit_clk active delay tri2actv - - 25 ns reset# inactive to bit_clk startup delay trst2clk 0.1628 - 400 m s bit_clk active to reset# asserted tclk2rst 0.416 - - m s parameter symbol min typ max units sync active high pulse width tsync_high 1.0 1.3 - m s sync inactive to bit_clk startup delay tsync2clk 162.8 - - ns tres_low trst2clk reset# bit_clk sdata_in ttri2actv ttri2actv figure 1. cold reset timing tsync_high tsync_2clk sync bit_clk figure 2. warm reset timing
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 18 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2.2.3. clocks note: 1) worst case duty cycle restricted to 45/55. parameter symbol min typ max units bit_clk frequency - 12.288 - mhz bit_clk period tclk_period - 81.4 - ns bit_clk output jitter - 750 - ps blt_clk high pulse width (note note:) tclk_high 36 40.7 45 ns bit_clk low pulse width (note note:) tclk_low 36 40.7 45 ns sync frequency - 48.0 - khz sync period tsync_period - 20.8 - m s sync high pulse width tsync_high - 1.3 - m s sync low_pulse width tsync_low - 19.5 - m s sync bit_clk tclk_high tclk_low tclk_period tsync_high tsync_period tsync_low figure 3. clocks timing
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 19 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2.2.4. stac9758/9759 crystal elimination circuit and clock frequencies the stac9758/9759 supports several clock frequency inputs as described in the following table. in general, when a 24.576mhz crystal is not used, the xtl_out pin should be tied to ground. this short to ground configures the part into an alternate clock mode and enables an on board pll. codec modes: p = the stac9758/9759 as a primary codec s = the stac9758/9759 as a secondary codec whenever pin 3 is pulled down, the codec will be in primary mode with the codec id 00 regard- less of the state of cid1 pin. the only secondary mode operation available is with external device sourcing bit_clk and codec id = 2. note: 1) pin #2 (xtl_in) may be left unconnected if codec is in secondary mode. table 1. clock mode configuration xtl_out pin config cid1 pin config clock source input codec mode codec id xtal float 24.576 mhz crystal p 0 short to ground float 14.31818 mhz source p 0 short to ground pulldown 48 mhz source p 0 xtal or open pulldown 12.288 mhz bit_clk s 2 table 2. common clocks and sources clock source clock frequency xtal 24.576 mhz bit_clk 12.288 mhz vga 14.31818 mhz usb 48 mhz
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 20 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2.2.5. data setup and hold (50 pf external load) note: setup and hold time parameters for sdata_in are with respect to the ac'97 controller. 2.2.6. signal rise and fall times (bit_clk: 75 pf external load; from 10% to 90% of vdd) (sdata_in: 60 pf external load; from 10% to 90% of vdd)) parameter symbol min typ max units setup to falling edge of bit_clk tsetup 10 - - ns hold from falling edge of bit_clk thold 10 - - ns parameter symbol min typ max units bit_clk rise time triseclk - - 6 ns bit_clk fall time tfallclk - - 6 ns sdata_in rise time trisedin - - 6 ns sdata_in fall time tfalldin - - 6 ns bit_clk t hold t setup sdata_out sdata_in sync tco v ih v il v oh v ol figure 4. data setup and hold timing bit_clk sdata_in tfallclk triseclk trisedin tfalldin figure 5. signal rise and fall times timing
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 21 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 2.2.7. ac-link low power mode timing 2.2.8. ate test mode note: all ac-link signals are normally low through the trailing edge of reset#. bringing sdata_out high for the trailing edge of reset# causes the stac9758/9759 ac-link outputs to go high impedance, which is suitable for ate in-circuit testing. once the test mode has been entered, the stac9758/9759 must be issued another reset# with all ac-link signals low to return to the normal operating mode. note: # denotes an active low signal. parameter symbol min typ max units end of slot 2 to bit_clk, sdata_in low ts2_pdown - - 1.0 m s parameter symbol min typ max units setup to trailing edge of reset# (also applies to sync) tsetup2rst 15.0 - - ns rising edge of reset# to hi-z delay toff - - 25.0 ns bit_clk sdata_in note: bit_clk not to scale ts2_pdown don't care data pr4 write to 0x20 slot 2 slot 1 sdata_out sync figure 6. ac-link low power mode timing tsetup2rst hi-z toff reset# sdata_out sdata_in, bit_clk figure 7. ate test mode timing
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 22 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 3. typical connection diagram figure 8. typical connection diagram see the reference design for additional connection information. note: if pin 48 is held high at powerup, register 28h (extended audio id), bit [2] will be held to zero, to indicate the spdif is not available. tie pin 48 to ground with a 10 k w resistor to ensure spdif is enabled. 0.1 f 1 f 0.1 f 0.1 f 10 f 0.1 f *suggested avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 mic2_l 16 mic2_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 820 pf 29 30 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 hp_out_r *terminate ground plane as close to codec as possible analog ground digital ground hp_out_l 39 37 mono_out 36 front_r 35 front_l 43 44 40 48 34 33 31 27 vrefout eapd/spdifi cid1 gpio3 28 47 46 45 11 reset# 10 sync 24 bit_clk sdata_out 5 6 8 27 pf 22 w emi filter 3.3v 5% 3.3v or 5v 5% tune to layout cap2 afilt1 afilt2 ctr lfe avss3 spdifo/adat gpio2 gpio1 gpio0 vref sdata_in stac9758 (5v analog) or stac9759 (3.3v analog) 1 f 32 *optional 0.1 f 1 f* 27 pf 27 pf 24.576 mhz clock_in* *add resistive divider when using 5v clock. (near clk source) 0 w optional
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 23 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 3.1. split independent power supply operation in pc applications, one power supply input to the stac9758/9759 may be derived from a supply regulator and the other directly from the pci power supply bus. when power is applied to the pc, the regulated supply input to the ic will be applied some time delay after the pci power supply. without proper on-chip partitioning of the analog and digital circuitry, some manufacturer's codecs would be subject to on-chip scr type latch-up. idt?s stac9758/9759 specifically allows power-up sequencing delays between the analog (avddx) and digital (vdddx) supply pins. these two power supplies can power-up independently and at differ- ent rates with no adverse effects to the codec. the ic is designed with independent analog and digi- tal circuitry that prevents on-chip scr type latch-up. see the reference design for additional connection information.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 24 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? figure 9. split independent power supply operation note: if pin 48 is held high at powerup, register 28h (extended audio id), bit [2] will be held to zero, to indicate the spdif is not available. tie pin 48 to ground with a 10 k w resistor to ensure spdif is enabled. 0.1 f 1 f 0.1 f 0.1 f 1 f 0.1 f 2 w * ferrite bead 3.3v 5% avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 2 3 27 pf 27 pf 24.576 mhz 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 16 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 cap2 32 *optional 0.1 f 1 f* 820 pf 29 30 afilt1 afilt2 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 hp_out_r *terminate ground plane as close to codec as possible analog ground digital ground hp_out_l 39 37 mono_out 36 35 43 44 40 avss3 48 34 33 31 1 f 27 vref vrefout eapd/spdifi cid1 gpio3 28 47 46 45 11 reset# 10 sync 24 sdata_in bit_clk sdata_out 5 6 8 stac9759 *optional 27 pf 22 w emi filter tune to layout clock_in* *add resistive divider when using 5v clock. (near clk source) 0 w optional mic2_l mic2_r front_r front_l ctr lfe spdifo/adat gpio2 gpio1 gpio0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 25 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 4. controller, codec and ac-link this section describes the physical and high-level functional aspects of the ac?97 controller to codec interface, referred to as ac-link. 4.1. ac-link physical interface the stac9758/9759 communicates with its companion digital controller via the ac-link digital serial interface. ac-link has been defined to support connections between a single controller and up to four codecs. all digital audio, modem, and handset data streams, as well as all control (com- mand/status) information are communicated over this serial interconnect, which consists of a clock (bit_clk), frame synchronization (sync), serial data in (sdata_in), serial data out (sdata_out), and a reset (reset#). 4.2. controller to single codec the simplest and most common ac?97 system configuration is a point-to-point ac-link connection between controller and the stac9758/9759 , as illustrated in figure 10. a primary codec may act as either a source or a consumer of the bit clock, depending on the con- figuration. while reset# is asserted, if a clock is present at the bit_clk pin for at least five cycles before reset# is de-asserted, then the codec is a consumer of bit_clk, and must not drive bit_clk when reset# is de-asserted. the clock is being provided by other than the primary codec, for instance by the controller or an independent clock chip. in this case the primary codec must act as a consumer of the bit_clk signal as if it were a secondary codec. this clock source detec tion must be done each time the reset# line is asserted. in the case of a warm reset, where the clock is halted but reset# is not asserted, the codec must remember the clock source, and not begin generating the clock on the assertion of sync if the codec had previ- ously determined that it was a consumer of bit_clk. sync digital dc'97 controller ac'97 codec bit_clk sdata_out sdata_in reset# xtal_in xtal_out figure 10. ac-link to its companion controller
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 26 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? the stac9758/9759 uses the xtal_out pin (pin 3) and the cid0 and cid1 pins (pins 45 & 46) to determine its alternate clock frequencies. see section 2.2.4: page19 for additional information on crystal elimination and for supported clock frequencies. if, when the reset# signal has been de-asserted, the codec has not detected a signal on bit_clk as defined in the previous paragraph then the ac?97 codec derives its clock internally from an externally attached 24.576 mhz crystal or oscillator, or optionally from an external 14.318mhz oscillator, and drives a buffered 12.288mhz clock to its digital companion controller over ac-link under the signal name ?bit_clk?. clock jitter at the dacs and adcs is a fundamental impediment to high quality output, and the internally generated clock will provide ac?97 with a clean clock that is independent of the physical proximity of ac?97?s companion digital controller (hence- forth referred to as ?the controller?). if bit_clk begins toggling while the reset# signal is still asserted, the clock is being provided by other than the primary codec, for instance by the controller or by a discrete clock source. in this case, the primary codec must act as a consumer of the bit_clk signal as if it were a secondary codec. the beginning of all audio sample packets, or audio frames, transferred over ac-link is synchro- nized to the rising edge of the sync signal. sync is driven by the controller. the controller gener- ates sync by dividing bit_clk by 256 and applying some conditioning to tailor its duty cycle. this figure 11. codec clock source detection ac'97 clock source detection reset# signal asserted bit_clk toggling? 12.288mhz signal on bit_clk is being generated externally; codec uses this signal as the clock. yes no after reset# signal deasserted 24.576mhz crystal present? 24.576mhz crystal on xtl_in and xtl_out used by codec to generate clock on bit_clk yes 24.576mhz oscillator present? no 24.576 mhz signal on xtl_in used by codec to generate 12.288mhz clock on bit_clk yes 14.318mhz oscillator presnent? no 14.318 mhz signal on xtl_in used by codec to generate 12.288mhz clock on bit_clk yes error condition - no clock source present no
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 27 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? yields a 48 khz sync signal whose period defines an audio frame. data is transitioned on ac-link on every rising edge of bit_clk, and subsequently sampled by the receiving device on the receiv- ing side of ac-link on each immediately following falling edge of bit_clk. 4.3. controller to multiple codec s several vendor specific methods of supporting multiple codec configurations on ac-link have been implemented or proposed, including codecs with selective ac-link pass-through and con- trollers with duplicate ac-links. potential implementations include: ? 6-channel audio using 3 x 2-channel codecs ? separate codecs for independent audio and modem afe ? docking stations, where one codec is in the laptop and another is in the dock this specification defines support for up to four codecs on the ac-link. by definition there can be one primary codec (id 00) and up to three secondary codecs (ids 01,10, and 11). the codec id functions as a chip select. secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers. multiple codec ac-link implementations must run off a common bit_clk. they can potentially save controller pins by sharing sync, sdata_out, and reset# from the ac?97 digital control- ler. each device requires its own sdata_in pin back to the controller. this prevents contention of multiple devices on one serial input line. support for multiple codec operation necessitates a specially designed controller. an ac?97 digi- tal controller that supports multiple codec configurations implements multiple sdata_in inputs, supporting one primary codec and up to three secondary codecs. 4.3.1. primary codec addressing primary ac?97 codecs respond to register read and write commands directed to codec id 00 f or details of the primary and secondary codec addressing protocols . primary devices must be con- figurable (by hardwiring, strap pin(s), or other methods) as codec id 00, and reflect this in the two-bit codec id field(s) of the extended audio and/or extended modem id register(s). the primary codec may either drive the bit_clk signal or consume a signal provided by the digi- tal controller or other clock generator. 4.3.2. secondary codec addressing secondary ac?97 codecs respond to register read and write commands directed to codec ids 01, 10, or 11. secondary devices must be configurable (via hardwiring, strap pin(s), or other meth- ods) as codec ids 01, 10, or 11 in the two-bit field(s) of the extended audio and/or extended modem id register(s). codecs configured as secondary must power up with the bit_clk pin configured as an input. using the provided bit_clk signal is necessary to ensure that everything on the ac-link is syn- chronous. bit_clk is the clock source (multiplied by 2 so that the internal rate is 24.576 mhz).
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 28 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 4.3.3. codec id strapping audio codecs in the 48-pin package use pins 45 and 46 (defined as id0# and id1#) as strapping (i.e. configuration) pins to configure the codec id. the id0# and id1# strapping bits adopt inverted polarity and default to 00 = primary (via a weak internal pullup) when left floating. this eliminates the need for external resistors for codecs configured as primary, and maintains backward compatibil- ity with existing layouts that treat pins 45 and 46 as ?no connect? or cap to ground. pulldowns are typically 0-10 k w and connected to digital (not analog) ground. the stac9758 is normally operated as primary, which id 00. pin 46 is used as cid1. pin 45 is used as gpio3. 4.4. clocking for multiple codec implementations to keep the system synchronous, all primary and secondary codec clocking must be derived from the same clock source, so they are operating on the same time base. in addition, all ac-link proto- col timing must be based on the bit_clk signal, to ensure that everything on the ac-link will be synchronous. as a secondary codec, the stac9758 uses the primary?s bit_clk output to derive 24.576 mhz. see section 2.2.4: page19 for clock frequencies supported and configurations. 4.5. stac9758/9759 as a primary codec the following clocking options are supported as a primary: ? 24.576 mhz crystal attached to xtal_in and xtal_out ? 24.576 mhz external oscillator provided to xtal_in ? 14.318 mhz external oscillator provided to xtal_in ? 48 mhz external oscillator provided to xtal_in see section 2.2.4: page19 for clock frequencies supported and configurations. 4.5.1. stac9758/9759 as a secondary codec the following clocking option is supported as a secondary: ? bit_clk input provided by the primary. in this mode, a clock at xtal_in (pin 2) is ignored and may b e left unconnected. see section 2.2.4: page19 for clock frequencies supported and configurations. table 3. recommended codec id strapping xtal_out (pin 3) pi n 46 pi n 45 configuration short to gnd na (freq select) na (gpio3) primary id 00 xtal nc na (gpio3) primary id 00 xtal pulldown na (gpio3) secondary id 01
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 29 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 4.6. ac-link power management 4.6.1. powering down the ac-link the ac-link signals can be placed in a low power mode. when ac?97?s powerdown register (26h) is programmed to the appropriate value, both bit_clk and sdata_in are brought to and held at a logic low voltage level. after signaling a reset to ac?97, the ac?97 controller should not attempt to play or capture audio data until it has sampled a codec ready indication from ac?97. bit_clk and sdata_in are transitioned low immediately following decode of the write to the pow- erdown register (26h) with pr4. when the ac?97 controller driver is at the point where it is ready to program the ac-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. after programming the ac?97 device to this low power, halted mode, the ac?97 controller is required to drive and keep sync and sdata_out low. once the ac?97 codec has been instructed to halt bit_clk, a special ?wake-up? protocol must be used to bring the ac-link to the active mode since normal audio output and input frames can not be communicated in the absence of bit_clk. 4.6.2. waking up the ac-link there are two methods for bringing the ac-link out of a low power, halted mode. regardless of the method, it is the ac?97 controller that performs the wake-up task. 4.6.2.1. controller initiates wake-up ac-link protocol provides for a ?cold ac?97 reset?, and a ?warm ac?97 reset?. the current power down state would ultimately dictate which form of ac?97 reset is appropriate. unless a ?cold? or ?reg- ister? reset (a write to the reset register) is performed (wherein the ac?97 registers are initialized to their default values), registers are required to keep state during all power down modes. once powered down, re-activation of the ac-link via re-assertion of the sync signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. when ac-link powers up, the codec indicates readiness via the codec ready bit (input slot0, bit15). sync bit_clk sdata_out note: bit_clk not to scale sdata_in tag write to 0x20 slot 2 per frame data pr4 tag slot 2 per frame figure 12. stac9758/9759 p owerdown timing
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 30 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 4.6.2.2. codec initiates wake-up the stac9758/9759 (running off vaux) can trigger a wake event (pme#) by transitioning sdata_in from low to high and holding it high until either a warm or cold reset is observed on the ac-link. this functionality is typically implemented in modem codecs that detect ring, caller id, etc. note that when the ac-link is either programmed to the low power mode or shut off completely, bit_clk may stop if the primary codec is supplying the clock, which shuts down the ac-link clock to the secondary codec 1 . in order for a secondary codec to react to an external event (phone ringing), it must support an independent clocking scheme for any pme# associated logic that must be kept alive when the ac-link is down. this includes logic to asynchronously drive sdata_in to a logic high-level which signals a wake request to the ac?97 digital controller. 4.6.3. codec reset there are three types of ac?97 reset: ? a cold reset where all ac?97 logic (most registers included) is initialized to its default state ? a warm reset where the contents of the ac?97 register set are left unaltered ? a register reset which only initializes the ac?97 registers to their default states 4.6.3.1. cold ac?97 reset a cold reset is achieved by asserting reset# (low) for the minimum specified time, then subse- quently de-asserting reset# (high). bit_clk and sdata_in will be activated, or re-activated as the case may be, and all ac?97 control registers will be initialized to their default power on reset val- ues. reset# is an asynchronous ac?97 input. 4.6.3.2. warm ac?97 reset a warm ac?97 reset will re-activate the ac-link without altering the current ac?97 register values. a warm reset is signaled by driving sync high for a minimum of 1ms in the absence of bit_clk. within normal audio frames, sync is a synchronous ac?97 input. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to ac?97. ac?97 must not respond with the activation of bit_clk until sync has been sampled low again by ac?97. this will preclude the false detection of a new audio frame. 4.6.3.3. register ac?97 reset all registers in an ac device can be restored to their default values by performing a write (any value) to the reset register, 00h. 1. secondary codec always configures its bit_clk pin as an input.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 31 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5. ac-link digital interface 5.1. overview ac-link is the 5 pin digital serial interface that links ac?97 codec to controller. the ac-link proto- col is a bi-directional, fixed clock rate, serial digital stream. ac-link handles multiple input and output pcm audio streams, as well as control register accesses employing a time division multiplexed (tdm) scheme that divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample re solution. the stac9758/9759 dacs, adcs, and spdif can be assigned to slots 3&4, 6&9, 7&8 or 10&11. figure 13. bi-directional ac-link frame with slot assignments table 4. ac-link output slots (transmitted from the controller) slot name description 0 sdata_out tag msbs indicate which slots contain valid data; lsbs convey codec id 1 control cmd addr write port read/write command bit plus 7-bit codec register address 2 control data write port 16-bit command register write data 3, 4 pcm l&r dac playback 20-bit pcm data for left and right channels 5 modem line 1 dac 16-bit modem data for modem line 1 output 6, 7, 8, 9 pcm center, surround l&r, lfe 20-bit pcm data for center, surround l&r, lfe channels pcm mic vendor rsvd vendor rsvd line2 adc hset adc vendor rsvd status addr outgoing streams (controller output - sdata_out) incoming streams (codec output - sdata_in) sync tag phase data phase pcm left cmd addr na pcm lsurr pcm lfe spdif tag cmd data pcm rt pcm ctr pcm rsurr spdif io ctrl pcm left line1 adc tag status data pcm rt io status slots 0 1 2 3 4 5 6 7 8 9 10 11 12 slot 12 can be used by the ac'97 codec if a modem codec is not present.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 32 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.2. ac-link serial interface protocol the ac?97 controller signals synchronization of all ac-link data transactions. the ac?97 codec, controller, or external clock source drives the serial bit clock onto ac-link, which the ac?97 control- ler then qualifies with a synchronization signal to construct audio frames. sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to support 12 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data (codec for out- going data and controller for incoming data) samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. if a slot is tagged invalid, it is the responsibility of the source of the data, (ac?97 codec for the input stream, ac?97 controller for the output stream), to stuff all bit positions with 0 during that slot?s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the ?tag phase?. the remainder of the audio frame where sync is low is defined as the ?data phase?. additionally, for power savings, all clock, sync, and data signals can be halted. this requires that an ac?97 codec be implemented as a static design to allow its register contents to remain intact when entering a power savings mode. 10 4 different uses a. 20-bit pcm data for spdif left channel b. extra slots for double rate audio for dac-a c. extra slots for double rate spdif c. modem line2 dac 11 4 different uses a. 20-bit pcm data for spdif right channel b. extra slots for double rate audio for dac-a c. extra slots for double rate spdif d. modem handset dac 12 modem io control gpio write port for modem control 12 codec irq can be used by codec if a modem codec is not present. table 5. the ac-link input slots (transmitted from the codec) slot name description 0 sdata_in tag msbs indicate which slots contain valid data 1 status addr read port msbs echo register address; lsbs indicate which slots request data 2 status data read port 16-bit command register read data 3, 4 pcm l&r adc record 20-bit pcm data from left and right inputs 5 modem line 1 adc not used by stac9758/9759 6-11 pcm adc record 20-bit pcm data - alternative slots for input 12 gpio status gpio read port and interrupt status table 4. ac-link output slots (transmitted from the controller) slot name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 33 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.2.1. ac-link variable sample rate operation the ac-link serial interconnect defines a digital data and control pipe between the controller and the codec. the ac-link supports 12 20-bit slots at 48 khz on sdata_in and sdata_out. the time division multiplexed (tdm) ?slot-based? architecture supports a per-slot valid tag infrastructure that the source of each slot?s data sets or clears to indicate the validity of the slot data within the cur- rent audio frame. this tag infrastructure can be used to support transfers between controller and codec at any sample rate. 5.2.2. variable sample rate signaling protocol ac-link?s tag infrastructure imposes fifo requirements on both sides of the ac-link. for example, in passing a 44.1 khz stream across the ac-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. does the ac?97 digital controller pass all 441 pcm samples followed by 39 invalid slots? or does the ac?97 digital controller evenly interleave valid and non-valid slots? each possible method brings with it different fifo requirements. to achieve interoperability between ac?97 digital controllers and codecs designed by different man- ufacturers, it is necessary to standardize the scheme for at least one side of the ac-link so that the fifo requirements will be common to all designs. the codec side of the ac-link is the focus of this standardization. the new standard approach calls for the addition of ?on demand? slot request flags. these flags are passed from the codec to the ac?97 digital controller during every audio input frame. each time the ac?97 digital controller sees one or more of the newly-defined slot request flags set active (low) in a given audio input frame, it knows that it must pass along the next pcm sample for the corre- sponding slot(s) in the ac-link output frame that immediately follows. the vra (variable rate audio) bit in the extended audio status and control register must be set to 1 to enable variable sample rate audio operation. setting the vra = 1 has two functions: 1. enables pcm dac/adc conversions at variable sample rates by write enabling sample rate registers 2c-34h. 2. enables the on demand codec-to-controller signaling protocol using slotreq bits that becomes necessary when a dac?s sample rate varies from the 48 khz ac-link serial frame rate the table below summarizes the behavior: note: if more than one codec is being used with the same controller dma engine, vra should not be used. for variable sample rate output, the codec examines its sample rate control registers, the state of its fifos, and the incoming sdata_out tag bits at the beginning of each ac-link output frame to determine which slotreq bits to set active (low). slotreq bits asserted during the current ac-link input frame signal which active output slots require data from the ac?97 digital controller in the next audio output frame. an active output slot is defined as any slot supported by the codec that is not in a power-down state. for fixed 48 khz operation the slotreq bits are always set active (low) and a sample is transferred in each frame. table 6. vra behavior ac?97 functionality vra = 0 vra = 1 slotreq bits always 0 (data each frame) 0 or 1 (data on demand) sample rate registers forced to 48 khz writable
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 34 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? for variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. thus, even in variable sample rate mode, the codec is always the master: for sdata_in (codec to controller), the codec sets the tag bit; for sdata_out (controller to codec), the codec sets the slotreq bit and then checks for the tag bit in the next frame. 5.2.2.1. slotreq behavior and power management slotreq bits for fixed rate, powered down, and all unsupported slots should be driven with 0 for maximum compatibility with the original ac '97 component specification. when a dac channel is powered down, it disappears completely from the serial frame: output tag and slot are ignored, and the slotreq bit is absent (forced to zero). when the controller wants to power-down a channel, all it needs to do is: 1. disable source of dac samples in controller 2. set pr bit for dac channel in registers 26h, 2ah, or 3eh when it wants to power-up the channel, all it needs to do is: 1. clear pr bit for dac channel in registers 26h, 2ah, or 3eh 2. enable source of dac samples in controller 5.2.3. primary and secondary codec register addressing the 2-bit codec id field in the lsbs of output slot 0 is an addition to the original ac-link protocol that enables an ac?97 digital controller to independently access primary and secondary codec registers. for primary codec access, the ac?97 digital controller: 1. sets the ac-link frame valid bit (slot 0, bit 15). 2. validates the tag bits for slot 1 and 2 command address and data (slot 0, bits [14:13] ). 3. sets a zero value (00) into the codec id field (slot 0, bits [1:0] ). 4. transmits the desired primary codec command address and command data in slots 1 and2. for secondary codec access, the ac?97 digital controller: 1. sets the ac-link frame valid bit (slot 0, bit 15). 2. invalidates the tag bits for slot 1 and 2 command address and data (slot 0, bits [14:13]). 3. places a non-zero value (01, 10, or 11) into the codec id field (slot 0, bits [1:0]). 4. transmits the desired secondary codec command address and command data in slots 1 and 2. secondary codecs disregard the command address and command data (slot 0, bits [14:13] ) tag bits unless they see a 2-bit codec id value (slot 0, bits [1:0] ) that matches their configuration. in a sense the secondary codec id field functions as an alternative valid command address (for sec- ondary reads and writes) and command data (for secondary writes) tag indicator. secondary codecs must monitor the frame valid bit, and ignore the frame (regardless of the state of the secondary codec id bits) if it is not valid. ac?97 digital controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the secondary codec id bits are set.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 35 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.3. ac-link output frame (sdata_out) the ac-link output frame data streams correspond to the multiplexed bundles of all digital output data targeting ac?97?s dac inputs, and control registers. as mentioned earlier, each ac-link output frame supports up to 12 20-bit outgoing data time slots. slot 0 is a special reserved time slot contain- ing 16-bits which are used for ac-link protocol infrastructure. figure 14 illustrates the time slot based ac-link protocol. figure 14. ac-link audio output frame a new ac-link output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the ac?97 codec samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the ac?97 con- troller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit posi- tion is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the ac?97 codec on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. figure 15. start of an audio output frame sdata_out?s composite stream is msb justified (msb first) with all non-valid slots? bit positions stuffed with 0 by the ac?97 controller. if there are less than 20 valid bits within an assigned and valid time slot, the ac?97 controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0. as an example, consider an 8-bit sample stream that is being played out to one of the stac9758/ 9759 dacs. the first 8-bit positions are presented to the dac (msb justified) followed by the next 12 bit-positions which are stuffed with 0 by the ac?97 controller. this ensures that regardless of the sync bit_clk sdata_out slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) cid1 cid0 valid "0" 19 19 "0" frame 19 "0" "0" sync bit_clk sdata_out slot1 slot2 end of previous audio frame valid frame sync asserted first sdata_out bit of frame
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 36 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? resolution of the implemented dac (16, 18 or 20-bit), no dc biasing will be introduced by the least significant bits. when mono audio sample streams are output from the ac?97 controller, it is necessary that both left and right sample stream time slots be filled with the same data. 5.3.1. slot 0: tag / codec id note: the dac can be assigned to slots 3&4, 6&9, 7&8, or 10&11. within slot 0, the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the ?valid frame? bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. the next 12 bit positions sampled by ac?97 indicate which of the corresponding 12 time slots contain valid data. in this way data streams of differing sample rates can be transmitted across ac-link at its fixed 48 khz audio frame rate. the two lsbs of slot 0 transmit the codec id used to distinguish primary and secondary codec register access. 5.3.2. slot 1: command address port the command port is used to control features, and monitor status (see ac-link input frame slots 1 and 2) for ac?97 codec functions including, but not limited to, mixer settings, and power manage- ment (refer to the control register section of this specification). the control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are currently defined, odd register (01h, 03h, etc.) accesses are reserved for future expansion. table 7. output slot 0 bit definitions bit description 15 frame valid 14 slot 1 primary codec valid command address bit (primary codec only) 13 slot 2 primary codec valid command data bit (primary codec only) slot 3-12 - slot-valid-data bits 12 slot 3: pcm left channel 11 slot 4: pcm right channel 10 slot 5: modem line 1 (not used on stac9758/9759) 9 slot 6: alternative pcm1 left 8 slot 7: alternative pcm2 left 7 slot 8: alternative pcm2 right 6 slot 9: alternative pcm1 right 5 slot 10: spdif left 4 slot 11: spdif right 3 slot 12: audio gpio 2 reserved (set to 0) 1-0 2-bit codec id field (00 reserved for primary; 01, 10, 11 indicate secondary)
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 37 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? note that shadowing of the control register file on the ac?97 controller is an option left open to the implementation of the ac?97 controller. the ac?97 codec?s control register file is nonetheless required to be readable as well as writeable to provide more robust testability. ac-link output frame slot 1 communicates control register address, and write/read command infor- mation to the stac9758/9759 . the first bit (msb) sampled by ac?97 indicates whether the current control transaction is a read or a write operation. the following 7 bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be stuffed with 0 by the ac?97 control- ler. 5.3.3. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the cur- rent command port operation is a write cycle (as indicated by slot 1, bit 19). ? bit(19:4) control register write data (stuffed with 0 if current operation is a read) ? bit(3:0) reserved (stuffed with 0) if the current command port operation is a read then the entire slot time must be stuffed with 0 by the ac?97 controller. 5.3.4. slot 3: pcm playback left channel ac-link output frame slot 3 is the composite digital audio left playback stream. in a typical ?games compatible? pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac?97 controller or host processor) with music synthesis output samples. if a sample stream of res- olution less than 20-bits is transferred, the ac?97 controller must stuff all trailing non-valid bit posi- tions within this time slot with 0. the dac can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.3.5. slot 4: pcm playback right channel ac-link output frame slot 4 is the composite digital audio right playback stream. in a typical ?games compatible? pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac?97 controller or host processor) with music synthesis output samples. if a sample stream of res- olution less than 20-bits is transferred, the ac?97 controller must stuff all trailing non-valid bit posi- tions within this time slot with 0. the dac can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.3.6. slot 5: modem line 1 output channel audio output frame slot 5 is reserved for modem operation and is not used by the stac9758/9759 . 5.3.7. slot 6 - 11: dac the dac can be assigned to slots 3&4, 6&9, 7&8, or 10&11. table 8. command address port bit assignments bit description comments 19 read/write command 1 = read, 0 = write 18:12 control register index sixty-four 16-bit locations, addressed on even byte boundaries 11:0 reserved stuffed with 0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 38 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.3.8. slot 12: audio gpio control channel ac-link output frame slot 12 contains the audio gpio control outputs. 5.4. ac-link input frame (sdata_in) the ac-link input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac?97 controller. as is the case for audio output frame, each ac-link input frame con- sists of 12 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits which are used for ac-link protocol infrastructure. the following diagram illustrates the time slot-based ac-link protocol. figure 16. stac9758/9759 audio input frame a new ac-link input frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the ac?97 codec samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the ac?97 codec transitions sdata_in into the first bit position of slot 0 (?codec ready? bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the ac?97 controller on the following falling edge of bit_clk. this sequence ensures that data transi- tions and subsequent sample points for both incoming and outgoing data streams are time aligned. figure 17. start of an audio input frame sdata_in?s composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0 by the ac?97 codec. sdata_in data is sampled on the falling edges of bit_clk. sync bit_clk sdata_in slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) valid "0" 19 19 "0" frame 19 "0" "0" "0" "0" sync bit_clk sdata_in slot1 slot2 end of previous audio frame codec ready sync asserted first sdata_out bit of frame
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 39 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.4.1. slot 0: tag within slot 0, the first bit is a global bit (sdata_in slot 0, bit 15) which flags whether the ac?97 codec is in the ?codec ready? state or not. if the ?codec ready? bit is a 0, this indicates that the ac?97 codec is not ready for normal operation. this condition is normal following the deasser- tion of power-on-reset for example, while the ac?97 codec?s voltage references settle. when the ac-link ?codec ready? indicator bit is a 1, it indicates that the ac-link and ac?97 codec control and status registers are in a fully operational state. codec must assert ?codec ready? within 400 m s after it starts receiving valid sync pulses from the controller, to provide an indication of con- nection to the link and that control/status registers are available for access. the ac`97 controller and related software must wait until all of the lower four bits of the control/status register, 26h, are set before attempting any register writes, or attempting to enable any audio stream, to avoid undesir- able audio artifacts. prior to any attempts at putting an ac?97 codec into operation the ac?97 controller should poll the first bit in the ac-link input frame (sdata_in slot 0, bit 15) for an indication that codec has gone ?codec ready?. once an ac?97 codec is sampled ?codec ready? 1 then the next 12 bit posi- tions sampled by the ac?97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data . 5.4.1.1. slot 1: status address port / slotreq signaling bits 1. there are several subsections within an ac?97 codec that can independently go busy/ready. it is the responsibility of the ac?97 controller to probe more deeply into the ac?97 codec?s register file to determine which subsections are actually ready. (see section 8.5. for e xtended codec registers page structure definition , on page 85 for more information.) table 9. input slot 1 bit definitions bit description 19 reserved (set to 0) 18-12 control register index echo (set to all 0 if tagged ?invalid? by ac?97 codec.) on demand data request flags for slots 11-2 (next output frame): 0 = send data 1 = do not send data 11 slot 3 request: pcm left channel 10 slot 4 request: pcm right channel 9 slot 5 request: reserved 8 slot 6 request: pcm center 7 slot 7 request: pcm left surround 6 slot 8 request: pcm right surround 5 slot 9 request: pcm lfe 4 slot 10 request: spdif 3 slot 11 request: spdif 2 slot 12 request: interrupt status and gpio 1, 0 reserved (set to 0) note: the adc can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 40 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.4.1.2. status address port the status port is used to monitor status for the stac9758/9759 functions including, but not limited to, mixer settings and power management. ac-link input frame slot 1s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged ?valid? by the ac?97 codec during slot 0.) the first bit (msb) generated by ac?97 is always stuffed with a 0. the following 7 bit positions com- municate the associated control register address, the next 10 bits support ac?97?s variable sample rate signaling protocol, and the trailing 2 bit positions are stuffed with 00 by ac?97. 5.4.1.3. slotreq signaling bits ac-link input frame slot #1, the status address port, now delivers codec control register read address and variable sample rate slot request flags for all output slots. ten of the formerly reserved least significant bits have been defined as data request flags for output slots 3-12. the ac-link input frame slot 1 tag bit is independent of the bit 11-2 slot request field, and only indicates valid status address port data (control register index). the codec should only set sdata_in tag bits for slot 1 (address) and slot 2 (data) to 1 when returning valid data from a previ- ous register read. they should otherwise be set to 0. slotreq bits have validity independent of the slot 1 tag bit. slotreq bits are always 0 in the following cases ? fixed rate mode (vra = 0) ? inactive (powered down) dac channel slotreq bits are only set to 1 by the codec in the following case ? variable rate audio mode (vra = 1) and active (power ready) dac and a non-48-khz dac sam- ple rate and codec does not need a sample 5.4.2. slot 2: status data port the status data port delivers 16-bit control register read data. if slot 2 is tagged invalid by ac?97, then the entire slot will be stuffed with 0 by ac?97. table 10. status address port bit assignments bit description comments 19 reserved stuffed with 0 18:12 control register index echo of register index for which data is being returned 11:2 slotreq see next section 1:0 reserved stuffed with 0 table 11. status data port bit assignments bit description comments 19:4 control register read data stuffed with 0 if tagged ?invalid? 3:0 reserved stuffed with 0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 41 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.4.3. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of stac9758/9759 input mux, post-adc. stac9758/9759 adcs are implemented to support 20-bit resolution. the adc can be assigned to slots 3&4, 6&9, 7&8, or 10&11. spdif_in can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.4.4. slot 4: pcm record right channel audio input frame slot 4 is the right channel output of stac9758/9759 i nput mux, post-adc. stac9758/9759 adcs are implemented to support 20-bit resolution. the adc can be assigned to slots 3&4, 6&9, 7&8, or 10&11. spdif_in can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.4.5. slot 5: modem line 1 adc audio input frame slot 5 is not used by the stac9758/9759 and are always stuffed with 0s. 5.4.6. slot 6-9: adc the left and right adc channels of the stac9758/9759 may be assigned to slots 6&9 by register 6eh. the adc can be assigned to slots 3&4, 6&9, 7&8, or 10&11. spdif_in can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.4.7. slots 7-8: vendor reserved the left and right adc channels of the stac9758/9759 may be assigned to slots 7&8 by register 6eh. the adc can be assigned to slots 3&4, 6&9, 7&8, or 10&11. spdif_in can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.4.8. slot 10 & 11: adc the left and right adc channels of the stac9758/9759 may be assigned to slots 10&11 by register 6eh. the adc can be assigned to slots 3&4, 6&9, 7&8, or 10&11. spdif_in can be assigned to slots 3&4, 6&9, 7&8, or 10&11 . 5.4.9. s lot 12: reserved ac-link input frame slot 12 contains the gpio status inputs and allows for audio interrupts. slot 12 can be used by the ac?97 codec if a modem codec is not present.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 42 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 5.5. ac-link interoperability requirements and recommendations 5.5.1. ?atomic slot? treatment of slot 1 address and slot 2 data command or status address and data cannot be split across multiple ac-link frames. the following transactions require that valid slot 1 address and valid slot 2 data be treated as ?atomic? (insepara- ble) with slot 0 tag bits for address and data set accordingly (that is, both valid): 1. ac?97 digital controller write commands to primary codecs 2. ac?97 codec status responses whenever the ac?97 digital controller addresses a primary codec, or an ac?97 codec responds to a read command, slot 0 tag bits should always be set to indicate actual slot 1 and slot 2 data validity. when the ac?97 digital controller addresses a secondary codec, the slot 0 tag bits for address and data must be 0. a non-zero, 2-bit, codec id in the lsbs of slot 0 indicates a valid read or write address in slot 1, and the slot 1 r/w bit indicates presence or absence of valid data in slot 2. 5.6. slot assignments for audio table 12. primary codec addressing: slot 0 tag bits function slot 0, bit 15 (valid frame) slot 0, bit 14 (valid slot 1 address) slot 0, bit 13 (valid slot 2 data) slot 0, bits 1-0 (codec id) ac?97 digital controller primary read frame n, sdata_out 1 1 0 00 ac?97 digital controller primary writeframe n, sdata_out 1 1 1 00 ac?97 codec status frame n+1, sdata_in 1 1 1 00 table 13. secondary codec addressing: slot 0 tag bits function slot 0, bit 15 (valid frame) slot 0, bit 14 (valid slot 1 address) slot 0, bit 13 (valid slot 2 data) slot 0, bits 1-0 (codec id) ac?97 digital controller secondary read frame n, sdata_out 1 0 0 01, 10, or 11 ac?97 digital controller secondary write frame n, sdata_out 1 0 0 01, 10, or 11 ac?97 codec status frame n+1, sdata_in 1 1 1 00
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 43 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? figure 18. bi-directional ac-link frame with slot assignments note: the dac & adc can be assigned to slots 3&4, 6&9, 7&8, or 10&11. t he ac-link output slots dedicated to audio are defined as follows: t he ac-link input slots dedicated to audio are defined as follows: table 14. ac-link slot definitions slot ad at channel name description 3 0 slot pair 1l 20-bit pcm data, typically front left channel 4 1 slot pair 1r 20-bit pcm data, typically front right channel 5 n/a not used not used 6 4 slot pair 3l 20-bit pcm data, typically center channel 7 2 slot pair 2l 20-bit pcm data, typically rear left channel 8 3 slot pair 2r 20-bit pcm data, typically rear right channel 9 5 slot pair 3r 20-bit pcm data, typically lfe channel 10 6 slot pair 4l 20-bit pcm data, typically spdif left channel 11 7 slot pair 4r 20-bit pcm data, typically spdif right channel 12 n/a interrupt control provides optional interrupt capability for audio codec (not usable when a modem is present) table 15. ac-link input slots dedicated to audio slot name description 3 slot pair 1l 20-bit pcm incoming data from left channel 4 slot pair 1r 20-bit pcm incoming data from right channel 5 not used not used 6 slot pair 3l 20-bit pcm incoming data from left channel 7 slot pair 2l 20-bit pcm incoming data from right channel 8 slot pair 2r 20-bit pcm incoming data from left channel pcm mic vendor rsvd vendor rsvd line2 adc hset adc vendor rsvd status addr outgoing streams (controller output - sdata_out) incoming streams (codec output - sdata_in) sync tag phase data phase pcm left cmd addr na pcm lsurr pcm lfe spdif tag cmd data pcm rt pcm ctr pcm rsurr spdif io ctrl pcm left line1 adc tag status data pcm rt io status slots 0 1 2 3 4 5 6 7 8 9 10 11 12 slot 12 can be used by the ac'97 codec if a modem codec is not present.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 44 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? the adc and the spdif inputs can be separately assigned to any of the four slot pairs. however, they cannot both be assigned to the same slot pair . 9 slot pair 3r 20-bit pcm incoming data from right channel 10 slot pair 4l 20-bit pcm incoming data from left channel 11 slot pair 4r 20-bit pcm incoming data from right channel 12 interrupt control provides optional interrupt capability for audio codec (not usable when a modem is present) table 16. audio interrupt slot definitions bit description 19-1 reserved (stac9758/9759 will return zeros in bits 19-1) 0 assertion = 1 will cause interrupt to be propagated to audio controller system interrupt. see register 24h definition for enabling mechanism. table 15. ac-link input slots dedicated to audio slot name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 45 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 6. stac9758/9759 m ixer ? mixer inputs ? analog pc beep, digital pc beep, phone, aux in, line in (has pre-select mux for jack sharing/ universal jacks tm ), mic in (mono and stereo modes - includes pre-select mux), dac-a, dac-b ? split-mute option on all stereo inputs allows left and right inputs to be muted independently. ? analog output sources ? dac-a, dac-b, dac-c, stereo mix, mono ? analog i/o ? pins 21/22, 23/24, 35/36, 39/41, 43/44 ? all analog i/o pins have analog jack sense ? pins 35/36 and 39/41 are capable of driving headphones ? all outputs are high impedance when powered down ? split-mute (bit d7) option on all outputs allows left and right outputs to be muted independently. 6.1. s pdif digital mux the stac9758/9759 incorporates a digital output that supports spdif formats. a multiplexer deter- mines which of two digital input streams are used for the digital output conversion process. these two streams include the pcm out data from the audio controller and the adc recorded output. the normal analog line_out signal can be converted to the spdif formats by using the internal adc to record the mix output, which is the combination of all analog and all digital sources. in the case of digital controllers with support for 4 or more channels, the spdif output mode can be used to sup- port compressed 6-channel output streams for delivery to home theater systems. these can be routed on alternate ac-link slots to the spdif output, while the standard 2-channel output is deliv- ered as selected by bits d5 and d4 in register 6eh. if the digital controller supports 6 channels, a spdif output with 4 analog channels can also be configured. if the digital controller has independent dma engines, spdif and analog can be used simulta- neously and independently. 6.2. spdif_in the stac9758 implements a multi-function pin in place of the traditional eapd pin (pin 47) . eapd functionality is supported as the default for compatibility with existing software. advanced implemen- tations can utilize this pin as an alternate gpio or spdif_in. a sophisticated digital pll allows automatic rate detection and accurate data recovery. the ability to accept consumer spdif voltage levels directly eliminates the need for costly external receiver ics. advanced features such as record slot select and spdif_in routing to the surround dacs allows simultaneous record and playback as well as multi-channel recording.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 46 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 6.3. adat optical ?lightpipe? support p in 48 can be switched to an alternate adat optical output mode to provide up to 8channels of royalty-free uncompressed 24-bit, 48 khz and 44.1 khz digital audio. an adat optical receiver is required to decode the data. this mode of operation is only intended for use with optical connections . 6.4. digital pc beep the stac9758/9759 offers 2 styles of pc beep, digital and analog. the digital pc beep is a new feature required by ac?97 2.3. this style of pc beep will eventually replace the analog style, thus eliminating the need for a pc beep pin. until this feature is widely accepted, all idt ac?97 2.3 codecs will provide both styles of pc beep. both pc beep styles use reg 0ah. additional informa- tion about register 0ah can be found in section8.2.5: page53. 6.5. double rate audi o dac-a (front) can be operated at double the normal sample rate. if the dra enable bit (reg 2a, bit d1) is set, dac-a will make use of an extra slot pair to provide twice the normal amount of data passed through ac-link, thus providing two samples per frame instead of one. slot pair 3&4 must be used for the primary slot pair. the secondary slot pair is defined by the drss bits (reg 20, bits d11:d10). if vra = 0 and dra = 1, then the output sample rate is fixed at 96 khz. if vra = 1 and dra = 1, then the output is double the rate specified in pcm dac rate, reg 2ch. 6.6. double rate spdif outpu t s pdif output can run at 96khz. if the dra enable bit (reg 2a, bit d1) is set, the spdif output will make use of an extra slot pair to provide twice the normal amount of data passed through ac-link, thus providing two samples per frame instead of one. slot pair 3&4 must be used for the primary slot pair. the secondary slot pair is defined by the spsa bits (reg 2a, bits d4:d5). double rate support for adat output is not present. adat output sample rates are limited to 48khz and 44.1khz. to simultaneously use double-rate audio and double-rate spdif output, the controller or driver must set drss and spsa bits to refer to the same set of secondary slots. the primary slot pair for either output will automatically be selected as 3&4 when the dra and drs bits are set. also, the controller or driver should make sure that pcm dac rate (reg 2ch) and spsr are set to equivalent values, since the slots are being shared.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 47 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 7. stac9758/9759 mixer diagram figure 19. stac9758/9759 mixer diagram 0ah 0ch 0eh 10h 12h 16h pc_beep cd aux 6eh:d12 pcmin 20h:d13 22h:d2-d3 20h:d9,d15 6ah:d1 mono_out 6eh: d5-d4 mux vol 06h mute 37 slot select ac link sdata_in slots 3,4,6,7,8,9,10,11 stereo adc 18,20 14,15 12 13 20h:d13 22h:d2-d3 phone 30 db s vol mute vol mute s mute vol vol vol mute mute vol mute 3d mux vol mute pins 16/17 digital pcbeep monoanalog stereoanalog digital key mux pins 39/41 pins 35/36 mux mux mux mux mux mux +3db hp mux slot select dac c (ctr/lfe) vol mute 36h slot select dac b (rear) 38h vol mute pins 23/24 pins 21/22 pins 43/44 18h vol mute vol mute 04h vol mute 14h ` mux mic mux mux line in mux 28h: d5-d4 slot select dac a (front) 3d 2ah:d5-d4 spdif output slot select slot select 48 mux adat lightpipe spdif_out/adat 0eh:d6 & 6eh:d2 mux mux left ch. mic right ch. mic left or right channel left or right channel 1ch vol mute +22 db -6db 1ah mux s -6db s -6db s -6db s 66h, page 00h:d2:d0 66h, page 00h:d5:d3 64h, page 00h:d15:d13 64h, page 00h:d12:d10 64h, page 00h:d9:d7 64h, page 00h:d6:d4 64h, page 00h:d3:d1 02h mux control 68h, page 00h, d0:1 mux control 68h, page 00h, d0:1 68h,page 00h:d8 slot select spdif receiver 47 spdif_in mux ac link sdata_in slots 3,4,6,7,8,9,10,11 spdif emable and select 68h page 00h, d12-11 68h, page 00h, d14-13 mic select: 20h:d8 stereo mic enable: 72h, page 0, d0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 48 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8. p rogramming registers 8.1. program register list table 17. programming register s address name default location 00h reset 6a90h 8.2.1; page50 02h master volume 8000h 8.2.2; page51 04h dac-a v olume 8000h 8.2.3; page52 06h master volume mono 8000h 8.2.4; page53 0ah pc beep v olume 0000h 8.2.5; page53 0ch phone v olume 8008h 8.2.7; page54 0eh m ono/stereo mic v olume 8008h 8.2.8; page56 10h line in v olume 8808h 8.2.8.2; page57 12h cd v olume 8808h 8.2.10; page59 14h dac-b to mixer2 v olume 8808h 8.2.11; page60 16h aux mixer volume 8808h 8.2.12; page62 18h pcm out mixer volume 8808h 8.2.13; page63 1ah record select 0000h 8.2.14; page64 1ch record gain 8000h 8.2.15; page65 20h general purpose 0000h 8.2.16; page66 22h 3d control 0000h 8.2.17; page67 24h audio int. & paging 0000h 8.2.18: page68 26h powerdown ctrl/stat 000fh 8.2.19; page70 28h extended audio id 0bc7h 8.2.20; page72 2ah extended audio control/status 05f0h 8.2.21; page74 2ch pcm dac rate (dac-a & dac-cl) bb80h 8.3.1; page77 2eh pcm surr dac rate (dac-b) bb80h 8.3.2; page77 30h pcm lfe dac rate (dac-cr) bb80h 8.3.3; page77 32h pcm lr adc rate bb80h 8.3.4; page78 36h center/lfe volume 8080h 8.3.5; page78 38h surround volume 8080h 8.3.6; page78 3ah spdif control 2000h 8.3.7; page79 3eh extended modem stat/ctl 0100h 8.4.4; page82 4ch gpio pin configuration 000fh 8.4.5; page82 4eh gpio pin polarity/type ffffh 8.4.6; page83 50h gpio pin sticky 0000h 8.4.7; page83 52h gpio pin mask 0000h 8.4.8; page84
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 49 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 54h gpio pin status 0000h 8.4.9; page84 60h spdif _ i n status 1 0000h 8.6.1; page86 60h (page 01h) codec class/rev 18xxh 8.6.2; page86 62h spdif_in status 2 0000h 8.6.3; page87 62h (page 01h) pci svid ffffh 8.6.4; page88 64h universal jacks tm output select d794h 8.6.3; page87 64h (page 01h) pci ssid ffffh 8.6.6; page89 66h universal jacks tm input select 0000h 8.6.5: page88 66h (page 01h) function select 0000h 8.6.8; page91 68h i/o misc. 0000h 8.6.7: page90 68h (page 01h) function information 0010h 8.6.10; page93 6ah digital audio control 0000h 8.6.9; page92 6ah (page01h) sense details n/a 8.6.12: page96 6ch revision code xxxxh 8.6.12; page96 6ch (page01h) dac slot mapping 3760h 8.6.14; page97 6eh analog special 1000h 8.6.14: page97 6eh (page01h) adc slot mapping 3000h 8.6.16; page100 70h idt reserved 0000h 8.6.17: page100 72h various functions 0000h 8.6.19: page102 74h eapd access 0800h 8.6.19: page102 76h analog misc. 0000h 8.6.20: page103 78h adat control and hpf b ypass 0000h 8.6.21: page103 7ah idt reserved 0000h 8.6.22: page103 7ch vendor id1 8384h 8.7.1; page104 7eh vendor id2 7658h 8.7.2; page104 table 17. programming register s (continued) address name default location
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 50 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2. program register descriptions 8.2.1. reset (00h) default: 6a90h writing any value to this register performs a register reset, which causes most registers to revert to their default values. this register reset also resets all the digital block. reading this register returns information about the part. d15 d14 d13 d12 d11 d10 d9 d8 rsrvd se4 se3 se2 se1 se0 id9 id8 d7 d6 d5 d4 d3 d2 d1 d0 id7 id6 id5 id4 id3 id2 id1 id0 bit(s) reset value r/w name description 15 0 ro reserved bit not used, should read back 0 14:10 11010 ro se4:se0 id for ss3d 9 1 ro id9 20-bit adc resolution ( supported) 8 0 ro id8 18-bit adc resolution 7 1 ro id7 20-bit dac resolution ( supported) 6 0 ro id6 18-bit dac resolution 5 0 ro id5 loudness / b ass boost (not supported ) 4 1 ro id4 headphone out ( supported) 3 0 ro id3 simulated stereo ( not supported) 2 0 ro id2 bass & treble control (not supported) 1 0 ro id1 reserve d 0 0 ro id0 dedicated mic pcm in channel (not supported)
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 51 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.2. master volume registers (02h) controls volume of stereo mix output. default: 8000h d15 d14 d13 d12 d11 d10 d9 d8 mute reserved ml5 ml4 ml3 ml2 ml1 ml0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved mr5 mr4 mr3 mr2 mr1 mr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, bit d6) if splitmute = 0 - b oth left and right channels are muted if splitmute = 1 - o nly the left channel is muted 14 0 ro reserved bit not used, should read back 0 13 0 wo ml5 if a 1 is written to this bit, then ml<4:0> is loaded with 1 1111b. this bit always reads 0. 12:8 0 rw ml<4:0> left lineout volume contro l 00h = 00000b = 0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation 7 0 rw rmute mutes right channel independ en t of left channel 0 = no m ute 1 = mut e the splitmute bit (reg 72, page 0, bit d6) must be set to 1 in order for the rmute bit to have an effect. the rmute bit is r/w, and may be written and read regardless of the state of the splitmute bit. 6 0 ro reserved bit n ot used, should read back 0 5 0 wo mr5 if a 1 is written to this bit, then mr<4:0> is loaded with 11111b. this bit always reads 0. 4:0 0 rw mr<4:0> right channel lineout volume control 00h = 00000b = 0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 52 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.3. dac-a volume register (04h) default: 8000h d15 d14 d13 d12 d11 d10 d9 d8 mute reserved ml5 ml4 ml3 ml2 ml1 ml0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved mr5 mr4 mr3 mr2 mr1 mr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, bit d6) if splitmute = 0 - b oth left and right channels are muted if splitmute = 1 - o nly the left channel is muted 14 0 ro reserved bit not used, should read back 0 13 0 wo ml5 if a 1 is written to this bit, then ml<4:0> is loaded with 11111b. this bit always reads 0. 12:8 0 rw ml<4:0> dac a left volume control 00h = 00000b = 0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation 7 0 rw rmute mutes right channel independent of left channel 0 = unmute 1 = muted the splitmute bit (reg 72 (page 0), d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w and may be written and read regardless of the state of the splitmute bit. 6 0 ro reserved bit not used, should read back 0 5 0 wo mr5 if a 1 is written to this bit, then mr<4:0> is loaded with 11111b. this bit always reads 0. 4:0 0 rw mr<4:0> dac a right volume control 00h = 00000b = 0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 53 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.4. master volume mono (06h) default: 8000h 8.2.5. pc beep volume (0ah) default: 0000 h d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved mm5 mm4 mm3 mm2 mm1 mm0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mut e mono output 14:6 0 ro reserved bit s not used, should read back 0 5 0 wo mm5 if a 1 is written to this bit, then mm<4:0> is loaded with 11111b. this bit always reads 0. 4:0 0 rw mm<4:0> mono volume control 00h = 00000 b = 0 d b attenuation 01h = 0 0001 b = - 1.5 db attenuation ..... 1fh = 11111 b = -4 6.5 db attenuation d15 d14 d13 d12 d11 d10 d9 d8 mute reserved pc_beep_fd f7 f6 f5 f4 f3 d7 d6 d5 d4 d3 d2 d1 d0 f2 f1 f0 pv3 pv2 pv1 pv0 rsrvd bit(s) reset value r/w name description 15 0 rw mute 0 = no mute 1 = mute pc beep signal 14 0 ro reserved bit not used, should read back 0 13 0 ro pc_beep_fd pc beep frequency divide 12:5 00h rw f[7:0] the beep frequency is the result of dividing the 48khz clock by 4 times the number specified in f[7:0] allowing tones from 47hz to 12khz. a value of 00h in bits f[7:0] disables internal pc beep generation and enables external pc beep input if available. 12:5 00h ro reserved bit not used, should read back 0 4:1 0 rw pv(3:0) pcbeep volume control 00h = 0000b = 0 db attenuation 00h = 0001b = -3 db attenuation ..... 0fh = 1111b = -45 db attenuation 0 0 ro reserved bit not used, should read back 0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 54 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.6. digital pc beep the ac?97 2.3 specification calls for the codec to generate a square wave tone at a particular vol- ume and frequency. typically, the bios will program this register during the power on self test (post) cycle. to create a tone using digital pc beep, write a non-zero value to the f bits in reg 0ah (bits d12:d5). the beep frequency is the result of dividing the 48khz clock by 4 times the number spec- ified in f[7:0], allowing tones from 47hz to 12khz. (see table18: page54). set the pv bits in reg 0ah, (bits d4:d1) control the volume level from 0 to 45db of attenuation in 3db steps. unmute bit d15 if necessary. to stop the tone, write 801fh to reg 0ah. this turns off the generator, turns the volume to the low- est setting, and mutes the register. applying a signal to the pc beep pin, pin 12, may cause the digital pc beep signal to become dis- torted or inaudible. when using the digital pc beep feature, leave the pc beep input pin connected to analog ground through a capacitor. connecting a capacitor from the pc beep input pin to ground will create a more pleasing sound by changing the digital output to a more sinusoidal like output. typically this feature will be used exclusively by the bios, and will not be used by controller or driver. 8.2.7. phone volume (0ch) default: 8008h. table 18. digital pc beep examples value reg 0ah [d12:d5] frequency 1 0x01 12,000hz 10 0x0a 1200hz 25 0x19 480 hz 50 0x32 240 hz 100 0x64 120 hz 127 0x0f 94.48 hz 255 0xff 47.05 hz d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gn4 gn3 gn2 gn1 gn0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute phone
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 55 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 14:5 0 ro reserved bits not used, should read back 0 4:0 08 rw gn<4:0> phone volume contro l 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0.0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation bit(s) reset value r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 56 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.8. mono/stereo mic volume (0eh) mic is actually one of 6 possible stereo input sources selected by the micmux (reg 66h, page 0, bits d2:d0). each of these sources may be selected as mono left, mono right, stereo, or stereo l-r swapped. boosts of 10, 20, or 30db are available to all inputs controlled by the microphone mux. 8.2.8.1. mic volume register in mono mode (default mode for reg 0eh) enabled when stereo mic enable bit (stmicen), reg 72h, page 0, bit d0 = 0 default: 8008h. d15 d14 d13 d12 d11 d10 d9 d8 allmute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved boosten reserved gn4 gn3 gn2 gn1 gn0 bit(s) reset value r/w name description 15 1 rw allmute mutes left and right channel mic 0 = no mute 1 = muted 14:8 0 ro reserved bit not used, should read back 0 7 0 rw rmute mutes right channel independent of left channel 0 = unmute 1 = muted the splitmute bit (reg 72, page 0, bit d6) and stmicen bit (reg 72, page 0, bit d0) must both be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute and stmicen bits. 6 0 rw boosten works with micgainval (register 6eh, bit d2) boosten micgainval 0 0 = 0 db 0 1 = 10 db 1 0 = 20 db 1 1 = 30 db 5 0 ro reserved bit not used, should read back 0 4:0 08 rw gn<4:0> mic volume control 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0.0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 57 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.8.2. mic volume register in stereo mode (reg 0eh) enabled when stereo mic enable bit (stmicen), reg 72h, page 0, bit d0 = 1 default: 8008h. d15 d14 d13 d12 d11 d10 d9 d8 lmute reserved gnl4 gnl3 gnl2 gnl1 gnl0 d7 d6 d5 d4 d3 d2 d1 d0 rmute boosten reserved gnr4 gn3 gnr2 gnr1 gnr0 bit(s) reset value r/w name description 15 1 rw lmute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, d6) if splitmute = 0 , both left and right channels are muted if splitmute = 1 , only the left channel is muted 14:13 0 ro reserved bit not used, should read back 0 12:8 0 rw gnl<4:0> stereo mic left volume contro l 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain ..... 1fh = 11111b = -34.5 db attenuation 7 0 rw rmute mutes right channel independ en t of left channel 0 = unmute 1 = mute d the splitmute bit (reg 72, page 0, bit d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute bit. 6 0 rw boosten turns on 20db of boost in the microphone preamp works in conjunction with micgainval (register 6eh, page 0, bit d2) which provides a 10db boost in the microphone preamp. boosten micgainval 0 0 = 0 db 0 1 = 10 db 1 0 = 20 db 1 1 = 30 db 5 0 ro reserved bit not used, should read back 0 4:0 0 rw gnr<4:0> stereo mic right channel volume control 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain ..... 1fh = 11111b = -34.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 58 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.9. line in volume (10h) default: 8808h. line_in may be assigned to one of 6 different pairs of input pins. see register 66h, page 0, for more info. d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gr0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved gr4 gr3 gr2 gr1 gr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, d6) if splitmute = 0 - b oth left and right channels are muted if splitmute = 1 - o nly the left channel is muted 14:13 0 ro reserved bit not used, should read back 0 12:8 08 rw gl<4:0> left linein volume contro l for stereo mix 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gai n (default) . .... 1fh = 11111b = -34.5 db attenuation 7 0 rw rmute mutes right channel independ en t of left channel 0 = unmute 1 = mute d the splitmute bit (reg 72 , page 0, d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute bit. 6:5 0 ro reserved bit not used, should read back 0 4:0 08 rw gr<4:0> right linein volume contro l for stereo mix 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 59 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.10. cd volume (12h) default: 8808h. d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gr0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved gr4 gr3 gr2 gr1 gr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, d6). if splitmute = 0 - both left and right channels are muted if splitmute = 1 - only the left channel is muted 14:13 0 ro reserved bit not used, should read back 0 12:8 08 rw gl<4:0> left cd volume control 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation 7 0 rw rmute mutes right channel independent of left channel 0 = unmute 1 = muted the splitmute bit (reg 72, page 0, d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute bit. 6:5 0 ro reserved bit not used, should read back 0 4:0 08 rw gr<4:0> right cd volume control 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 60 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.11. dac-b to mixer2 volume control (14h) default: 8808h. 8.2.11.1. video in use the stac9758 video_in path to the mixer (including the volume control of register 14h) is used by dac-b. the video_in pins are redefined as the second microphone input. however, the video input functionality can be implemented by the flexible input/output structure of the stac9758, called universal jacks. this technology allows for selectable input paths. the stac9758 has a line in mux that can select a variety of input options. using the line in mux to d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gr0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved gr4 gr3 gr2 gr1 gr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, d6). if splitmute = 0, both left and right channels are muted if splitmute = 1, only the left channel is muted 14:13 0 ro reserved bit not used, should read back 0 12:8 08 rw gl<4:0> dac-bl volume control 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation 7 0 rw rmute mutes right channel independent of left channel 0 = unmute 1 = muted the splitmute bit (reg 72, page 0, d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute bit. 6:5 0 ro reserved bit not used, should read back 0 4:0 08 rw gr<4:0> dac-br volume control 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 61 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? select pin 16 and 17, this will set up an extra line in that can be used as video in. line in will still be available using the standard pins 23 and 24, and its volume will be controlled by register 02h. ? use the same pins for video (pins 16&17) ? use the universal jack input select register (66h), bits d10:8 = 000b to select line in on pin 16/17 ? volume will be controlled by register 10h (as video is acting as line in) ? the line in slider now will control video. ? recording is done by using the line in record function in the record select register (1ah), by setting the left and/or right channel input select to line in ? left line in select d10:d8 = 100b ? right line in select d2:d0 = 100b ? unfortunately, the stac9758 cannot mix line in and video at the same time using pins 16 and 17 as line in for video is the easiest method to use video in on the stac9758. the alternative is to use pins 16&17 as mic, and, using the registers listed above, simple select the bit values to the desired input source.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 62 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.12. aux volume (16h) default: 8808h. d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gr0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved gr4 gr3 gr2 gr1 gr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, d6) . if splitmute = 0 - b oth left and right channels are muted if splitmute = 1 - o nly the left channel is muted 14:13 0 ro reserved bit not used, should read back 0 12:8 08 rw gl<4:0> left aux volume contro l 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation 7 0 rw rmute mutes right channel independ en t of left channel 0 = unmute 1 = mute d the splitmute bit (reg 72 (page 0), d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute bit. 6:5 0 ro reserved bit not used, should read back 0 4:0 08 rw gr<4:0> right aux volume contro l 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 63 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.13. pcmout volume (18h) default: 8808h. note: wdm drivers normally leave reg 18h set to 0808h (unity gain). it does not change during the windows session. instead, the windows software mixer adjusts the wave volume digitally. d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gr0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved gr4 gr3 gr2 gr1 gr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, d6) . if splitmute = 0 - b oth left and right channels are muted if splitmute = 1 - o nly the left channel is muted 14:13 0 ro reserved bit not used, should read back 0 12:8 08 rw gl<4:0> left pcm volume contro l 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation 7 0 rw rmute mutes right channel independ en t of left channel 0 = unmute 1 = mute d the splitmute bit (reg 72 (page 0), d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute bit. 6:5 0 ro reserved bit not used, should read back 0 4:0 08 rw gr<4:0> right pcm volume contro l 00h = 00000b = +12.0 db gain 01h = 00001b = +10.5 db gain ..... 08h = 01000b = 0 db - unity gain (default) ..... 1fh = 11111b = -34.5 db attenuation
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 64 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.14. record select (1ah) default: 0000h (corresponding to mic in) used to select the record source independently for right and left. d15 d14 d13 d12 d11 d10 d9 d8 reserved sl2 sl1 sl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved sr2 sr1 sr0 bit(s) reset value r/w name description 15:11 0 ro reserved bits not used, should read back 0 10:8 0 rw sl2:s left channel input select 00h = 000b = mic mux this selects the output of the micmux (reg 66h) if r eg 20h, bit d8 = 0 then m i c l if reg 20h, bit d8 = 1 then mic r 0 01 = cd in (left) 010 = not implemented (mute input to mux) 0 11 = aux in (left) 100 = line in mux ( left ) t his selects the output of the lineinmux (reg 66h) 101 = stereo mix (left) 110 = mono mix 111 = phone 7:3 0 ro reserved bits not used, should read back 0 2:0 0 rw sr2:sr0 right channel input selec t 00h = 000b = mic mux this selects the output of the micmux (reg 66h) if reg 20h, bit d8 = 0 then mic r if reg 20h, bit d8 = 1 then mic l 0 01 = cd in (right) 010 = not implemented (mute input to mux) 011 = aux in (right) 100 = l ine in mux (right) this selects the output of the lineinmux (reg 66h) 101 = stereo mix (right) 110 = mono mix 111 = phone
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 65 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.15. record gain (1ch) default: 8000h (corresponding to 0 db gain with mute on) note: most signals coming from external line-level sources will not need any additional gain. signals coming from the micmux (see reg 66h) will have the mic boost values (0, 10, 20, or 30 db) added to the values indicated by the gl and gr bits in reg 1ch d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 rmute reserved gr3 gr2 gr1 gr0 bit(s) reset value r/w name description 15 1 rw mute 0 = no mute 1 = mute the channels to be affected are determined by the splitmute bit (reg 72, page 0, d6) . if splitmute = 0 - b oth left and right channels are muted if splitmute = 1 - o nly the left channel is muted 14:12 0 ro reserved bits not used, should read back 0 11:8 0 rw gl<3:0> left adc v olume control 00h = 0000 = 0 db gain 01h = 0001 = + 1.5 db gain .... 0fh = 1111 = + 22.5 db gain 7 0 rw rmute mutes right channel independ en t of left channel 0 = unmute 1 = mute d the splitmute bit (reg 72 (page 0), d6) must be set to 1 in order for the rmute bit to have an effect on the sound. the rmute bit is r/w. the rmute bit may be written and read regardless of the state of the splitmute bit. 6:4 0 ro reserved bits not used, should read back 0 3:0 0 rw gr<3:0> right adc v olume control 00h = 0000 = 0 db gain 01h = 0001 = +1.5 db gain .... 0fh = 1111 = +22.5 db gain
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 66 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.16. general purpose (20h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 pop reserved 3d reserved drss1 drss0 mix ms d7 d6 d5 d4 d3 d2 d1 d0 loopback reserved bit(s) reset value r/w name description 15 0 rw pop pop bypass disables dac-a digital 3d only. this ensures that a recording of the dac (through stereo mix) does not perform the 3d processing twice. 14 0 ro reserved bit not used, should read back 0 13 0 rw 3d 0 = 3d effect disabled 1 = 3d effect enabled 12 0 ro reserved bit not used, should read back 0 11:10 00 rw drss <1:0> dac-a d ouble rate slot selec t rate slot select 00: pcm l, r n+1 data is on slots 10-11 (default) 01: pcm l, r n+1 data is on slots 7, 8 10: reserved 11: reserved 9 0 rw mix mono output select (0 = mix, 1 = mic) 8 0 rw ms mic select / mic swa p 7 0 rw loopback 1 = enables adc to dac loop back test 0 = loopback disabled each adc output will go to all 3 dac pairs . 6:0 0 ro reserved bits not used, should read back 0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 67 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.17. 3d control (22h) default: 0000h this register is used to control the 3d stereo enhancement function, idt surround 3d (ss3d), built into the ac'97 component. note that register bits dp3-dp2 are used to control the separation ratios in the 3d control for line_out. ss3d provides for a wider soundstage extending beyond the nor- mal 2-speaker arrangement. note that the 3d bit in the general purpose register (20h) must be set to 1 to enable ss3d functionality to allow the bits in 22h to take effect. the three separation ratios are implemented. the separation ratio defines a series of equations that determine the amount of depth difference (high, medium, and low) perceived during two-channel playback. the ratios provide for options to narrow or widen the soundstage. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved dp3 dp2 reserved bit(s) reset value r/w name description 15:4 0 ro reserved bits not used, should read back 0 3:2 0 rw dp3,dp2 line_out separation ratio dp3 dp2 effect 0 0 0 ( off ) 0 1 3 ( low ) 1 0 4.5 ( med ) 1 1 6 ( high ) 1:0 0 ro reserved bits not used, should read back 0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 68 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.18. audio interrupt and paging (24h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 i4 i3 i2 i1 i0 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved pg3 pg2 pg1 pg0 bit(s) reset value r/w name description 15 0 rw i4 0 = interrupt is clear 1 = interrupt is set interrupt event is cleared by writing a 1 to this bit. the interrupt bit will change regardless of condition of interrupt enable (i0) status. an interrupt in the gpi in slot 12 in the aclink will follow this bit change when interrupt enable (i0) is unmasked. 14-13 0 ro i3-i2 interrupt cause 00 = reserved 01 = sense cycle complete, sense info available. 10 = change in gpio input status 11 = sense cycle complete and change in gpio input status. these bits will reflect the general cause of the first interrupt event generated. it should be read after interrupt status has been confirmed as interrupting. the information should be used to scan possible interrupting events in proper pages. 12 0 rw i1 sense cycle 0 = sense cycle not in progress 1 = sense cycle start. writing a 1 to this bit causes a sense cycle start if supported. if sense cycle is not supported this bit is read only. 11 0 rw i0 interrupt enable 0 = interrupt generation is masked. 1 = interrupt generation is un-masked. the driver should not un-mask the interrupt unless ensured by the ac?97 controller that no conflict is possible with modem slot 12 - gpi functionality. some ac?97 2.2 compliant controllers may not support audio codec interrupt infrastructure. in either case, software should poll the interrupt status after initiating a sense cycle and wait for sense cycle max delay to determine if an interrupting event has occurred.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 69 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 10:4 0 ro reserved bits not used, should read back 0 3:0 0 rw pg3:pg0 page selector 00h = vendor specific 01h = page id 01 (see section8.6: page85 for additional information on the paging registers) 02h-0fh = reserved pages this register is used to select a descriptor of 16 word pages between registers 60h to 6fh. value 0h is used to select vendor specific space to maintain compatibility with ac?97 2.2 vendor specific registers. system software determines implemented pages by writing the page number and reading the value back. all implemented pages must be consecutive. (i.e., page 2h cannot be implemented without page 1h). bit(s) reset value r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 70 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.19. powerdown ctrl/stat (26h) default: 000fh d15 d14 d13 d12 d11 d10 d9 d8 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 d7 d6 d5 d4 d3 d2 d1 d0 reserved ref anl dac adc bit(s) reset value r/w name description 15 0 rw eapd 1 = forces eapd pad to vdd 0 = forces eapd pad to gnd 14 0 rw pr6 0 = headphone amplifier powered up 1 = headphone amplifier powered down 13 0 rw pr5 0 = digital clk active 1 = digital clk disable. 12 0 rw pr4 0 = digital active 1 = powerdown: pll, ac-link, crystal oscillator; forced low: bit clock, sdata_in disabled: dsp clk, spdif clk 11 0 rw pr3 0 = vag/ vref and vrefout are active 1 = vag/v ref and vrefout are powered down, and pr2 is asserted in analog block 10 0 rw pr2 0 = analog active 1 = all signal path analog is powered down (vrefout and vag still on, user should set pr0, pr1, pr6 prior to setting pr2) 9 0 rw pr1 0 = all dacs powered up 1 = all dacs powered down pr1 is the global dac power down , and powers down all dacs. pr1 is ored with respective pr1, prj, prk and pr_dac_a bits 8 0 rw pr0 0 = adc powered up 1 = adc powered down 7:4 0 ro reserved bit not used, should read back 0 3 1 ro ref v ref status 1 = vref?s enabled 2 1 ro anl a nalog mixers, etc. status 1 = analog mixers ready. 1 1 ro dac d ac status 1 = dac ready to playback (front dac only) the pr_dac_a bit is used to independently power down dac-a 0 1 ro adc a dc status 1 = adc ready to record
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 71 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.19.1. ready status the lower half of this register is read-only status, a 1 indicating that each subsection is ?ready?. ready is defined as the subsection's ability to perform in its nominal state. when this register is writ- ten, the bit values that come in on ac-link will have no effect on read-only bits 0-7. when the ac-link ?codec ready? indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ac-link and ac'97 control and status registers are in a fully operational state. the ac'97 controller must further probe this power down control/status register to determine exactly which subsec- tions, if any are ready. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. 8.2.19.2. powerdown controls t he stac9758/9759 is capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). see the section ?low power modes? for more information. 8.2.19.3. external amplifier power down control output the eapd bit 15 of the powerdown control/status register (index 26h) directly controls the output of the eapd output, pin 47, and produces a logical 1 when this bit is set to logic high. this function is used to control an external audio amplifier power down. eapd = 0 places approximately 0v on the output pin, enabling an external audio amplifier. eapd = 1 places approximately dvdd on the output pin, disabling the external audio amplifier. audio amplifiers that operate with reverse polarity will require an external inverter to maintain software driver compatibility. eapd can also act as a gpio or spdif_in. see section 8.4.1: page81. the gpio controls in section8.4: page81 have no effect on eapd.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 72 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.20. extended audio id (28h) default: 0bc7h the extended audio id register is a read only register except for bits d4 and d5. id1 and id0 echo the configuration of the codec as defined by the programming of pin 46 externally. id0 is always a 0 for the 9758. code 00 returned defines the codec as the primary codec, while code 10 identi- fies the codec as the secondary codec. the amap bit, d9, will return a 1 indicating that the codec supports the optional ac?97 2.3 compliant ac-link slot to audio dac mappings. the default condition assumes that 00 are loaded in the dsa0 and dsa1 bits of the extended audio id (index 28h). with 0 in the dsa1 and dsa0 bits, the codec slot assignments are as per the ac?97 specifi- cation recommendations. if the dsa1 and dsa0 bits do not contain 0, the slot assignments are as per the table in the section describing the extended audio id (index 28h). the vra bit, d0, will return a 1, indicating that the codec supports the optional variable sample rate conversion as defined by the ac?97 specification. note: 1. external cid pin status (from analog) these bits are the logical inversion of the pin polarity (pin 46). these bits are zero if xtal_out is grounded with an alternate external clock source in primary mode only. secondary mode can either be through bit clk driven or 24mhz clock driver, with xtal_out floating. note: 2. if pin 48 is held high at powerup, register 28h (extended audio id) bit [2] will be held to zero, to indicate the spdif is not available. tie pin 48 to ground with a 10k w resistor to ensure spdif is enabled. d15 d14 d13 d12 d11 d10 d9 d8 id1 id0 reserved rev1 rev0 amap ldac d7 d6 d5 d4 d3 d2 d1 d0 sdac cdac dsa1 dsa0 reserved spdif dra vra bit reset value r/w name function 15:14 00 or 10 ro id [1,0] 00 = xtal_out grounded (note 1) cid1#, cid0# = xtal_out crystal or floating 13:12 00 ro reserved bits not used; should read back 00 11:10 10 ro rev[1:0] indicates codec is ac?97 rev 2.3 compliant 9 1 ro amap multi-channel slot support (always = 1) 8 1 ro ldac low frequency effect dac supported 7 1 ro sdac surround dacs supported 6 1 ro cdac center channel dac supported 5:4 00 rw dsa [1,0] dac slot assignment see dsa table below. the dsa bits for dac-a are ignored when double rate audio dra is used. slots 3&4 are used instead. the drss bits indicate which secondary slots to use. dac-b and dac-c are unaffected by the dra bit. 3 0 ro reserved reserved 2 1 ro spdif 0 = spdif pulled high on reset, spdif disabled 1 = default, spdif enabled (note 2) 1 1 ro dra double rate audio supported 0 1 ro vra variable sample rates supported (always = 1)
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 73 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? amap defaults codec id function dac1 dac2 dac3 spdif all 6-ch primary w/ spdif 3 & 4 7 & 8 6 & 9 10 & 11 dsa assignment table dsa1, dsa0 dacs 1,2 dacs 3,4 dacs 5,6 00 (default) 3&4 7&8 6&9 01 7&8 6&9 10&11 10 6&9 10&11 3&4 11 10&11 3&4 7&8
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 74 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.21. extended audio control/status (2ah) default: 05f0h note: if pin 48 is held high at powerup, the spdif is not available and bits d15:d1 can not be written and will read back zero. d15 d14 d13 d12 d11 d10 d9 d8 vcfg reserved prk prj pri spcv reserved ldac d7 d6 d5 d4 d3 d2 d1 d0 sdac cdac spsa1 spsa0 rsrvd spdif dra vra enable bit(s) reset value r/w name description 15 0 rw vcfg determines the spdif transmitter behavior when data is not being transmitted. when asserted, this bit forces the deassertion of the spdif ?validity? flag, which is bit 28 transmitted by the spdif sub-frame. the ?v? bit is defined in the spdif control register (reg 3ah). if "v" = 1 and "vcfg" = 0, then for each spd if sub-frame (left & right), bit [28] "validity" flag reflects whether or not an internal codec transmission error has occurred. specifically an internal codec error should result in the "validity" flag being set to "1". if "v" = 0 and "vcfg" = 1, in the case where the spd if transmitter does not receive a valid sample from the ac'97 controller, (left or right), the spd if transmitter should set the "validity" flag to "0" and pad the "audio sample word" with "0"s for sub-frame in question. if a valid sample (left or right) was received and successfully transmitted, the "validity" flag should be "0" for that sub-frame. default state, coming out of reset, for "v" and "v cfg " should be 0 and 0. these bits should be settable via driver .inf options. 14 0 ro reserved reserved 13 0 rw prk 0 = pcm lfe dacs on 1 = pcm lfe dacs off 12 0 rw prj 0 = pcm surround dacs on 1 = pcm surround dacs off 11 0 rw pri 0 = pcm center dac on 1 = pcm center dac off 10 1 ro spcv 0 = invalid spdif configuratio n 1 = valid spdif configuration 9 0 ro reserved reserved 8 1 ro ldac 0 = pcm lfe dac is not ready 1 = pcm lfe dac is read y 7 1 ro sdac 0 = pcm surround dac is not ready 1 = pcm surround dac is ready 6 1 ro cdac 0 = pcm center dac is not ready 1 = pcm center dac is ready
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 75 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.2.21.1. variable rate audio enable the extended audio status control register also contains one active bit to enable or disable the variable sampling rate capabilities of the dacs and adcs. if vra enable ( reg 20h, bit d0) is 1, the variable sample rate control registers (2ch, 2eh, 30h, and 32h) are active, and ?on-demand? slot data required transfers are allowed. if the vra bit is 0, the dacs and adcs will operate at the default 48 khz data rate. the stac9758/9759 supports ?on-demand? slot request flags. these flags are passed from the codec to the ac?97 controller in every audio input frame. each time a slot request flag is set (active low) in a given audio frame, the controller will pass the next pcm sample for the corresponding slot in the audio frame that immediately follows. the vra enable bit must be set to 1 to enable ?on-demand? data transfers. if the vra enable bit is not set, the codec will default to 48khz trans- 5:4 11 rw spsa1:spsa0 spdif slot assignmen t 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 the drs (double rate spdif) bit causes the primary data to be taken from slots 3&4. the secondary data is taken from the slots indicated by spsa. if spsa bits are set to 00 (slot pair 3/4) and drs bit (double rate spdif) is set to 1, then the 20-bit data to dac-a will be doubled. this will not sound particularly bad, but is an operating mode which provides little benefit . 3 0 ro reserved reserved 2 0 rw spdif 0 = disables spdif (spdif_out is high z ) 1 = enable spdif spdif is a control bits for reg 3ah. this bit must be set low, i.e. spdif disabled, in order to write to reg 3ah bits d15,d13:d0. 1 0 rw dra double rate audi o 0 = disabled 1 = enabled when dra bit is set, then the dsa bits (reg 28, bits d5:d4) have no effect. d ata from pcm l and pcm r in output slots 3 and 4 is used in conjunction with pcm l (n+1) and pcm r (n+1) data , to provide dac streams at twice the sample rate designated by the pcm front sample rate control register. t he slots on which the (n+1) data is transmitted on is indi ca ted by the drss[1:0] bits in the general purpose register 20h. note that dra can be used without vra, in that case the converter rates are forced to 96 khz if dra = 0. 0 0 rw vra enable variable rate audio enabl e 0 = di sable d d ac and adc set to 48 khz reg 2ch, reg 2eh, reg 30h & reg 32h all read back b b80h 1 = enabled r eg 2 ch , reg 2eh, reg 30h & reg 32h control the various dac and adcsample rates bit(s) reset value r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 76 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? fers and every audio frame will include an active slot request flag. data is transferred every frame in this case. for variable sample rate output, the codec examines its sample rate control registers, the state of the fifos, and the incoming sdata_out tag bits at the beginning of each audio output frame to determine which slotreq bits to set active (low). slotreq bits are asserted during the current audio input frame for active output slots which will require data in the next audio output frame. for variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. thus, even in variable sample rate mode, the codec is always the master: for sdata_in (codec to controller), and the codec sets the tag bit. for sdata_out (controller to codec), the codec sets the slotreq bit and then checks for the tag bit in the next frame. whenever vra is set to 0 the pcm rate registers (2ch, 2eh, 30h, and 32h) are overwritten with bb80h (48khz). 8.2.21.2. spdif output the spdif bit in the extended audio status control register is used to enable and disable the spdif output functionality within the stac9758/9759 . if the spdif output bit is set to a 1, then the spdif output function is enabled. 8.2.21.3. spcv (spdif output configuration valid) the spcv bit is read-only and indicates whether or not the spdif output system is set up correctly. when spcv is 0, it indicates the system configuration is invalid. when spcv is 1, it indicates the system configuration is valid. 8.2.21.4. spsa1, spsa0 (spdif output slot assignment) spsa1 and spsa0 combine to provide the slot assignments for the spdif output data. stac9758/ 9759 is amap compliant as per the following table. 8.3. pcm dac rate registers the internal sample rate for the dacs and adcs are controlled by the value in these read/write reg- isters. each register contains a 16-bit unsigned value between 0 and 65535 which represents the conversion rate in hz. in vra mode (reg 2ah bit d0 = 1), if the value written to these registers is supported, that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample rate is sup- ported and returned. per pc 99 / pc 2001 specification, independent sample rates are supported for record and playback. whenever vra is set to 0, all pcm dac and adc rate registers will be loaded with bb80h (48khz). table 19. amap c ompliant amap defaults codec id function dac1 dac2 dac3 spdif all 6-ch primary w/ spdif 3 & 4 7 & 8 6 & 9 10 & 11
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 77 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? if vra is set to a 0, any write to this address will be ignored and the rate remains at 48khz. 8.3.1. pcm dac rate (2ch) controls dac-a (front) and dac-cl (center) default: bb80h ( see table20: page77 ) 8.3.2. pcm surround dac rate (2eh) controls dac-b (surround) default: bb80h ( see table20: page77 ) 8.3.3. pcm lfe dac rate (30h) controls dac-cr (lfe) default: bb80h ( see table20: page77 ) table 20. hardware supported sample rates sample rate sr15-sr0 value 8.000 khz 1f40h 11.025 khz 2b11h 16.000 khz 3e80h 22.050 khz 5622h 32.000 khz 7d00h 44.100 khz ac44h 48.000 khz bb80h d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 78 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.3.4. pcm lr adc rate (32h) default: bb80h ( see table20: page77 ) 8.3.5. center/lfe volume (36h) default: 8080h 8.3.6. surround volume (38h) default: 8080h d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved lfe5 lfe4 lfe3 lfe2 lfe1 lfe0 d7 d6 d5 d4 d3 d2 d1 d0 mute reserved cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 bit(s) reset value r/w name description 15 1 rw mute 0 = lfe not muted 1 = lfe muted 14 0 ro reserved bit not used, should read back 0 13 0 wo lfe5 if a 1 is written to this bit, then lfe<4:0> is loaded with 11111b. this bit always reads 0. 12:8 0 rw lfe[4:0] 00h = 00000b = 0.0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation 7 1 rw mute 0 = center not muted 1 = center muted 6 0 ro reserved bit not used, should read back 0 5 0 wo cnt5 if a 1 is written to this bit, then cnt<4:0> is loaded with 11111b. this bit always reads 0. 4:0 0 rw cnt[4:0] 00h = 00000b = 0.0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation d15 d14 d13 d12 d11 d10 d9 d8 mute reserved lsr5 lsr4 lsr3 lsr2 lsr1 lsr0 d7 d6 d5 d4 d3 d2 d1 d0 mute reserved rsr5 rsr4 rsr3 rsr2 rsr1 rsr0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 79 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.3.7. spdif control (3ah) default: 2000h bit(s) reset value r/w name description 15 1 rw mute 0 = left surround not muted 1 = left surround muted 14 0 ro reserved bit not used, should read back 0 13 0 wo lsr5 if a 1 is written to this bit, then lsr<4:0> is loaded with 11111b. this bit always reads 0. 12:8 0 rw lsr[4:0] 00h = 00000b = 0.0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation 7 1 rw mute 0 = right surround not muted 1 = right surround muted 6 0 ro reserved bit not used, should read back 0 5 0 wo rsr5 if a 1 is written to this bit, then rsr<4:0> is loaded with 11111b. this bit always reads 0. 4:0 0 rw rsr[4:0] 00h = 00000b = 0.0 db attenuation 01h = 00001b = -1.5 db attenuation ..... 1fh = 11111b = -46.5 db attenuation d15 d14 d13 d12 d11 d10 d9 d8 v drs spsr1 spsr2 l cc6 cc5 cc4 d7 d6 d5 d4 d3 d2 d1 d0 cc3 cc2 cc1 cc0 pre copy /audio pro
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 80 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? bit(s) reset value r/w name description 15 0 rw v validity: this bit affects the "validity" flag, bit [28] transmitted in each spd if subframe, and enables the spd if transmitter to maintain connection during error or mute conditions. subframe bit [28] = 0 indicates that data is valid for conversion at the receiver, 1 indicates invalid data (not suitable for conversion at the receiver). if "v" = 1, then each spd if subframe (left & right) should have bit [28] "validity" flag = 1 or set based on the assertion or de-assertion of the ac '97 "vforce" bit within the extended audio status and control register (d15, register 2ah) . 14 0 rw drs double rate spdif 0 = not enabled 1 = enable s spdif sample rates of 64 khz , 88.2 khz , and 96 khz w hen drs is enabled , t he spd if transmitter uses ac-link slots 3&4 plus the slot pair specified in the spsa bits (reg 2a, bits d5:d4) t o supply data at fs=64khz, 88.2khz or 96khz. a total of four slots are used for a stereo pair when operating in this mode. the first stereo pair to be played is contained in slots 3&4, and the second pair is contained in the slots specified by the spsa bits. t he spcv bit must indicate a valid configuration. the stac9758/9759 a utomatically determine s the correct channel status bits for fs from drs and spsr and insert s them as necessary. the controller or driver should p erform write followed by read to determine if drs is supported. 13:12 10 rw spsr[1,0] spdif and adat sample rate: 00 - 44.1khz rate 01 - reserved 10 - 48khz rate (default) 11 - 32khz rate when drs (d14 is set) , spdif (but not adat) will operate at : 00 - 88.2khz 01 - reserved 10 - 9 6 khz (def aul t) 11 - 64khz 11 0 rw l generation level is defined by the iec standard, or as appropriate . 10:4 0 rw cc[6, 0] category code is defined by the iec standard or as appropriate by media. 3 0 rw pre 0 = 0 m sec pre-emphasis 1 = pre-emphasis is 50/15 m sec 2 0 rw copy 0 = copyright not asserted 1 = copyright is asserted 1 0 rw /audio 0 = pcm data 1 = non-audio or non-pcm format 0 0 rw pro 0 = consumer use of the channel 1 = professional use of the channel
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 81 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.4. general purpose input & outputs 8.4.1. eapd eapd can act as a gpio, but is unaffected by the following registers. to use eapd as a gpio, use register 74h, the eapd access register located in section 8.6.19: page102. additional informa- tion about eapd can also be found in section 8.2.19.3: page71. 8.4.2. gpio pin definitions gpio pins are programmable to have input/output functionality. the data values (status) for these pins are all in one register with input/output configuration in a separate register. control of gpio pins configured for output is achieved by setting the corresponding bit in output slot 12; status of gpio pins configured for input is returned on input slot 12. the codec must constantly set the gpio pins that are configured for output, based upon the value of the corresponding bit position of the control slot 12. the codec should ignore output slot 12 bits that correspond to gpio control pins config- ured as inputs. the codec must constantly update status on input slot 12, based upon the logic level detected at each gpio pin configured for input. a gpio output pin value that is written via slot 12 in the current frame won?t affect the gpio status that is returned in that particular write frame. this slot 12-based control/status protocol minimizes the latency and complexity, especially for host-based controllers and host data pump software, and provides high speed monitoring and con- trol, above what could be achieved with command/status slots. for host-based implementations, most ac?97 registers can be shadowed by the driver in order to provide immediate response when read by the processor, and gpio pins configured as inputs should be capable of triggering an inter- rupt upon a change of status. the ac-link request for gpio pin status is always delayed by at least one frame time. read-mod- ify-writes across the ac-link will thus incur latency issues and must be accounted for by the soft- ware driver or ac?97 digital controller firmware. pci retries should be kept to a minimum wherever possible. 8.4.3. gpio pin implementation the gpios are set to a high impedance state on power-on or a cold reset. it is up to the ac?97 digi- tal controller to first enable the output after setting it to the desired state. gpio0 and gpio1 are on pins 33 and 34 (respectively) and are powered from the analog supply. when using these pins in an application, care must be taken to reduce the risk of injecting noise into the analog section. also, gpio0 and gpio1 will not be available when the analog supply is removed.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 82 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.4.4. extended modem status and control register (3eh) default: 0100 h 8.4.5. g pio pin configuration register (4ch) default: 000fh d15 d14 d13 d12 d11 d10 d9 d8 reserved pra d7 d6 d5 d4 d3 d2 d1 d0 reserved gpio bit(s) reset value r/w name description 15:9 0 ro reserved bit not used, should read back 0 8 1 rw pra 0 = gpio powered up / enabled 1 = gpio powered down / disabled 7:1 0 ro reserved bit not used, should read back 0 0 0 ro gpio 0 = gpio not ready (powered down) 1 = gpio ready (powered up) (this is just bit d8 inverted) d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gc3 (gpio3) gc2 (gpio2) gc1 (gpio1) gc0 (gpio0) bit(s) reset value r/w name description 15:4 0 ro reserved bit not used, should read back 0 3 1 rw gc3 0 = gpio3 configured as output 1 = gpio3 configured as input 2 1 rw gc2 0 = gpio2 configured as output 1 = gpio2 configured as input 1 1 rw gc1 0 = gpio1 configured as output 1 = gpio1 configured as inpu t 0 1 rw gc0 0 = gpio0 configured as output 1 = gpio0 configured as inpu t
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 83 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.4.6. gpio pin polarity/type register (4eh) default: ffffh 8.4.7. gpio pin sticky register (50h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gp3 (gpio3) gp2 (gpio2) gp1 (gpio1) gp0 (gpio0) bit(s) reset value r/w name description 15:4 fffh ro reserved bit not used, should read back 0 3 1 rw gp3 0 = gpio3 input polarity inverted, cmos output drive. 1 = gpio3 input polarity non-inverted, open-drain output drive. 2 1 rw gp2 0 = gpio2 input polarity inverted, cmos output drive. 1 = gpio2 input polarity non-inverted, open-drain output drive. 1 1 rw gp1 0 = gpio1 input polarity inverted, cmos output drive. 1 = gpio1 input polarity non-inverted, open-drain output drive. 0 1 rw gp0 0 = gpio0 input polarity inverted, cmos output drive. 1 = gpio0 input polarity non-inverted, open-drain output drive. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gs3 (gpio3) gs2 (gpio2) gs1 (gpio1) gs0 (gpio0) bit(s) reset value r/w name description 15:4 0 ro reserved bit not used, should read back 0 3 0 rw gs3 0 = gpio3 non-sticky configuration. 1 = gpio3 sticky configuration. 2 0 rw gs2 0 = gpio2 non-sticky configuration. 1 = gpio2 sticky configuration. 1 0 rw gs1 0 = gpio1 non-sticky configuration. 1 = gpio1 sticky configuration. 0 0 rw gs0 0 = gpio0 non-sticky configuration. 1 = gpio0 sticky configuration.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 84 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.4.8. gpio pin mask register (52h) default: 0000h 8.4.9. gpio pin status register (54h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gw3 (gpio3) gw2 (gpio2) gw1 (gpio1) gw0 (gpio0) bit(s) reset value r/w name description 15:4 0 ro reserved bit not used, should read back 0 3 0 rw gw3 0 = gpio3 interrupt not passed to gpio_int slot 12. 1 = gpio3 interrupt is passed to gpio_int slot 12. 2 0 rw gw2 0 = gpio2 interrupt not passed to gpio_int slot 12. 1 = gpio2 interrupt is passed to gpio_int slot 12. 1 0 rw gw1 0 = gpio1 interrupt not passed to gpio_int slot 12. 1 = gpio1 interrupt is passed to gpio_int slot 12. 0 0 rw gw0 0 = gpio0 interrupt not passed to gpio_int slot 12. 1 = gpio0 interrupt is passed to gpio_int slot 12. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gi3 (gpio3) gi2 (gpio2) gi1 (gpio1) gi0 (gpio0) bit(s) reset value r/w name description 15:4 0 ro reserved bit not used, should read back 0 3 x rw gi3 reads back value on gpio3. writing 0 will clear gpio3 sticky bit if set and enabled. writing 1 does nothing. 2 x rw gi2 reads back value on gpio2. writing 0 will clear gpio2 sticky bit if set and enabled. writing 1 does nothing. 1 x rw gi1 reads back value on gpio1. writing 0 will clear gpio1 sticky bit if set and enabled. writing 1 does nothing. 0 x rw gi0 reads back value on gpio0. writing 0 will clear gpio0 sticky bit if set and enabled. writing 1 does nothing.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 85 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.5. e xtended codec registers page structure definition registers 60h-68h are the extended codec registers. these registers allow for the definition of further capabilities. these bits provide a paged address space for extended codec information. the page selector bits in the audio interrupt and paging register (register 24h bits 3:0) control the page of information viewed through this page window. 8.5.1. extended registers page 00 page 00 of the extended codec registers is reserved for vendor specific use. driver writers should not access these registers unless the vendor id register has been checked first to ensure that the vendor of the ac '97 component has been identified and the usage of the vendor defined registers understood. 8.5.2. extended registers page 01 the usage of page 01 of the extended codec registers is defined in register 24h found in section8.2.18: page68. 8.5.3. extended registers page 02, 03 pages 02 and 03 of the extended codec registers are reserved for future use. 8.6. stac9758/9759 paging registers the ac?97 specification rev 2.3 uses a paging mechanism in order to increase the number of regis- ters. the registers currently used in the paging are 60h to 6eh. additional information about the extended codec registers, please refer to section 8.5: page85. one of two pages can be made active at any time, set in register 24h. register 24h is the audio interrupt and paging register. additional details about register 24h is located in section 8.2.18: page68. ? if page 00h is active, registers 60h to 6eh are vendor specific. ? if page 01h is active, registers 60h to 6eh have the following functionality: reg name function location 60h codec class/revision provides the codec class and a vendor specified revision identifier. 8.6.2: page86 62h pci svid allows for population by the system bios to identify the pci sub system vendor id. 8.6.4: page88 64h pci ssid allows for population by the system bios to identify the pci sub system id. 8.6.6: page89 66h function select provides the type of audio function being selected and which jack conductor the selected value is measured from. 8.6.8: page91 68h function information includes information about gain, inversion, buffer delays, information validity, and function information presence. 8.6.10: page93 6ah sense register includes information about the connector/jack location, input verses output sensing, the order of the sense results, and the specifc sense results. 8.6.12: page96
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 86 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.1. spdif_in status 1 r egister (60h, page 00h ) register 24h must be set to page 00h to access this register. default:0000h first of 2 registers that echo the status bits taken from the spdif input stream header. all bits relate directly to the defined header bits for iec60958. no translation or inversion necessary. 8.6.2. codec class/rev (60h page 01h ) register 24h must be set to page 01h to access this register. default: 18xxh 6ch dac slot mapping allows the controlling software to modify the default slot to the dac mappings. 8.6.14: page97 6eh adc slot mapping allows the controlling software to modify the default slot to the adc mappings. 8.6.16: page100 d15 d14 d13 d12 d11 d10 d9 d8 lvl cc6 cc5 cc4 cc3 cc2 cc1 cc0 d7 d6 d5 d4 d3 d2 d1 d0 mode1 mode0 pre2 pre1 pre0 cpy /aud pro bit(s) reset value r/w name description 15 0 ro lvl generation level 14:8 0 ro cc<6:0> category code iec spec ? the category code indicates the kind of equipment that generates the digital audio interface signal.? 7:6 0 ro mode<1:0> mode 5:3 0 ro pre<2:0> pre emphesis 2 0 ro cpy copy 1 0 ro /aud non pcm / pcm 0 = pcm data 1 = non pcm (ac3). if spdif is routed to dac-b, this will mute dac-b. 0 0 ro pro professional / consumer 0 = consumer 1 = professional d15 d14 d13 d12 d11 d10 d9 d8 reserved cl4 cl3 cl2 cl1 cl0 d7 d6 d5 d4 d3 d2 d1 d0 rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 reg name function location
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 87 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.3. spdif_in status 2 r egister (62h, page 00h ) register 24h must be set to page 00h to access this register. second of two registers that echo the status bits from the sdata_in header. default: 0000h bit(s) reset value r/w name description 15:13 0 ro reserved reserved-not defined 12:8 * ro cl4:cl0 codec compatibility class (ro) this is a codec vendor specific field to define software compatibility for the codec. software read this field together with codec vendor id (reg 7c-7eh) to determine vendor specific programming interface compatibility. software can rely on vendor specific register behavior to be compatible among vendor codecs of the same class. 00h - field not implemented. 01h-1fh - vendor specific compatibility class code 7:0 ** ro rv7:rv0 revision id: (ro) this register specifies a device specific revision identifier. the value is chosen by the vendor. zero is an acceptable value. this field should be viewed as a vendor defined extension to the codec id. this number changes with new codec stepping of the same codec id. d15 d14 d13 d12 d11 d10 d9 d8 sp_val reserved ca1 ca0 fs3 fs2 fs1 fs0 d7 d6 d5 d4 d3 d2 d1 d0 cn3 cn2 cn1 cn0 sn3 sn2 sn1 sn0 bit(s) reset value r/w name description 15 0 ro sp_val 0 = spdif valid 1 = spdif invali d validity: this bit affects the "validity" flag, bit[28] transmitted in each spdif subframe, and enables the spdif transmitter to maintain connection during error or mute conditions. subframe bit[28] = 0 indicates that data is valid for conversion at the receiver, 1 indicates invalid data (not suitable for conversion at the receiver) . if either spdif subframe bit[28] validity flag = 1, then this field is set to invalid, equal 1. 14 0 ro reserved bit not used, should read back 0 13:12 00 ro ca<1:0> clock accuracy 00 = level ii 01 = level i 10 = level iii 11 = reserved 11:8 0000 ro fs<3:0> sample rate 0000 = 44.1 khz 0100 = 48 khz 1100 = 32 khz all other combinations are reserved and shall not be used until further defined (iec spec).
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 88 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.4. pci svid (62h page 01h ) register 24h must be set to page 01h to access this register. default: ffffh 8.6.5. universal jack tm output select (64h, page 00h ) register 24h must be set to page 00h to access this register. default: d794h 7:4 0 ro cn<3:0> channel number (audio channel) 0000 = do not take into account 1000 = a (left channel for stereo channel format) 0100 = b (right channel for stereo channel format) 1100 = c .......... 1111 = o 3:0 0 ro sn<3:0> source number 0000 = do not take into account 1000 = 1 0100 = 2 1100 = 3 ......... 1111 = 15 d15 d14 d13 d12 d11 d10 d9 d8 pvi15 pvi14 pvi13 pvi12 pvi11 pvi10 pvi9 pvi8 d7 d6 d5 d4 d3 d2 d1 d0 pvi7 pvi6 pvi5 pvi4 pvi3 pvi2 pvi1 pvi0 bit(s) reset value r/w name description 15:0 ffffh rw pvi15:pvi0 pci sub system vendor id: this field provides the pci sub system vendor id of the audio or modem sub assembly vendor (i.e., cnr manufacturer, motherboard vendor). this is not the codec vendor pci vendor id, nor the ac '97 controller pci vendor id. if data is not available, returns ffffh. d15 d14 d13 d12 d11 d10 d9 d8 csen cs1 cs0 rsen rs1 rs0 fsen fs1 d7 d6 d5 d4 d3 d2 d1 d0 fs0 lsen ls1 ls0 msen ms1 ms0 reserved bit(s) reset r/w name description 15 1 rw csen pin 43/44 output enable (0 = pad powered down) 14:13 10 rw cs[1:0] pins 43/44 (?center/lfe? in default 6ch mode) 00 = front (dac-a)..........volume = 0x04 01 = rear (dac-b)...volume = 0x38 10 = ctr/lfe (dac-c)...volume = 0x36 11 = mixer out.......volume = 0x02 12 1 rw rsen pin 39/41 output enable bit(s) reset value r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 89 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? each output capable pin can have 4 sources: dac-a, dac-b, dac-c, and mixer out. each may be disabled/high-z for use as an input. the 3 select bits work as follows: 8.6.6. p ci ssid (64h page 01h ) register 24h must be set to page 01h to access this register. default: ffffh 11:10 01 rw rs[1:0] pins 39/41 (?rear? in 6ch default mode ) 00 = front (dac-a).........volume = 0x04 01 = rear (dac-b)...volume = 0x38 10 = ctr/lfe (dac-c)...volume = 0x36 11 = mixer out.......volume = 0x02 9 1 rw fsen pin 35/36 output enable (0 = pad powered down) 8:7 11 rw fs[1:0] line_out = pins 35/36 00 = front (dac-a)..........volume = 0x04 01 = rear (dac-b)..volume = 0x38 10 = ctr/lfe (dac-c)...volume = 0x36 11 = mixer out.........volume = 0x02 6 0 rw lsen pin 23/24 output enable 5:4 01 rw ls[1:0] line-in = pins 23/24 00 = front (dac-a)....... .volume = 0x04 01 = rear (dac-b)...volume = 0x38 10 = ctr/lfe (dac-c)...volume = 0x36 11 = mixer out.......volume = 0x02 3 0 rw msen pin21/22 output enable (0 = pad powered down) 2:1 10 rw ms{1:0] mic = pins 21/22 00 = front (dac-a)..........volume = 0x04 01 = rear (dac-b)..volume = 0x38 10 = ctr/lfe (dac-c)...volume = 0x36 11 = mixer out.........volume = 0x02 0 0 ro reserved bit not used, should read back 0 xsen xs1 xs0 resource volume control register 1 0 0 front (dac-a) 0x04 1 0 1 rear (dac-b) 0x38 1 1 0 ctr/lfe (dac-c) 0x36 1 1 1 mixer out 0x02 0 x x disabled d15 d14 d13 d12 d11 d10 d9 d8 pi15 pi14 pi13 pi12 pi11 pi10 pi9 pi8 d7 d6 d5 d4 d3 d2 d1 d0 pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 bit(s) reset value r/w name description 15:0 ffffh rw pi15:pvi0 pci: this field provides the pci sub system id of the audio or modem sub assembly (i.e., cnr model, motherboard sku). this is not the codec vendor pci id, nor the ac '97 controller pci id. information in this field must be available for ac '97 controller reads when codec ready is asserted in ac link. if data is not available, returns ffffh. bit(s) reset r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 90 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.7. u niversal jack tm i nput select (66h, page 00h ) register 24h must be set to page 00h to access this register. default: 0201h d15 d14 d13 d12 d11 d10 d9 d8 reserved li2 li1 li0 d7 d6 d5 d4 d3 d2 d1 d0 reserved mi2 mi1 mi0 bit(s) reset value r/w name description 15:11 0 ro reserved bit not used, should read back 0 10:8 010 rw li[2:0] line input selector determines which pair of input pins is routed to the input of the line in section 00h = 000b = pins 16 & 17 mic2_l, mic2_r 01h = 001b = pins 21 & 22 mic1_l, mic1_r 02h = 010b = pins 23 & 24 line_in_l, line_in_r 03h = 011b = pins 35 & 36 front_l, front_r 04h = 100b = pins 39 & 41 surr_l, surr_r 05h = 101b = pins 43 & 44 ctr, lfe 06h = 110b = mute 07h = 111b = mute 7:3 0 ro reserved bit not used, should read back 0 2:0 001 rw mi[2:0] mi crophone input selecto r determines which pair of input pins is routed to the input of the microphone preamp 00h = 000b = pins 16 & 17 mic2_l, mic2_r 01h = 001b = pins 21 & 22 mic1_l, mic1_r 02h = 010b = pins 23 & 24 line_in_l, line_in_r 03h = 011b = pins 35 & 36 front_l, front_r 04h = 100b = pins 39 & 41 surr_l, surr_r 05h = 101b = pins 43 & 44 ctr, lfe 06h = 110b = mute 07h = 111b = mute
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 91 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.8. function select (66h page 01h ) register 24h must be set to page 01h to access this register. default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved fc3 fc2 fc1 fc0 t/r bit(s) reset source r/w reset value name description 15-5 n/a ro 0 reserved bit not used, should read back 0 4-1 reset rw 00h fc3:fc0 function code bits: 00h - line out (master out) 01h - head phone out (aux out) 02h - dac 3 (c/lfe) 03h - spdif out 04h - phone in 05h - mic1 (mic select =0) 06h - mic2 (mic select =1) 07h - line in 08h - cd in 09h - video in 0ah - aux in 0bh - mono out 0ch - spdif in 0dh - vref out 0e-0fh - reserved for supported jack and mic sense functions, see table22: page96. the function code bits are used to read register 68h (page 01h) and register 6ah (page01h). mono i/o should report relevant sense and function information on tip, and report not supported on ring. this is true for the following function codes: 0bh (mono out) and 0eh (spdif out) setting the function code to unsupported values will return a 0 when accessing the information valid bit in page 01 register 68h bit 5. 0 reset r/w 0 t/r tip or ring selection bit. this bit sets which jack conductor the sense value is measured from. software will program the corresponding the ring/tip selector bit together with the i/o number in bits fc[3:0]. 0 - tip (left) 1 - ring (right)
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 92 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.9. i/o misc. (68h, page 00h ) register 24h must be set to page 00h to access this register. default: 2001h d15 d14 d13 d12 d11 d10 d9 d8 noblkchk spis a1 spis a0 spi_selen1 spi_selen0 vi amute hp3db d7 d6 d5 d4 d3 d2 d1 d0 p48 mo p47 m1 p47 m0 dcs dbs das hp selen1 hp selen0 bit(s) reset value r/w name description 15 0 rw noblkchk 0 = normal behavior 1 = disable block size checking for spdif_in. this is needed primarily for testing so short blocks can be sent to result in quicker pll_locked assertion. 14:13 01 rw spisa<1:0> spdif_in slot select 00 = slots 3/4 01 = slots 7/8 10 = slots 6/9 11 = slots 10/11 12:11 00 rw spi selen <1:0> spdif_in select and enable 00 = spdif input powered down 01 = spdif input to ac link 10 = spdif input to dac 2 11 = spdif input to both aclink and dac 2 10 0 rw vi 0 = respond to spdif_in valid tag 1 = ignore spdif_in valid tag 9 0 rw amute disable 0 = auto mute when spdif stream marked non pcm 1 = auto mute disabled. 8 0 rw hp3db headphone +3db boost 0 = 3db off 1 = 3db on 7 0 rw p48 m0 pin 48 configuration 0 = spdif out 1 = adat out 6:5 00 rw p47 m1:m0 pin 47 configuration 00 = eapd output/gpio 01 = no function 10 = spdif input (special buffer for low level signals) 11 = spdif input (standard input for high level signals) 4 0 rw dcs dac-c channel swap 0 = normal operation 1 = center and lfe swapped 3 0 rw dbs dac-b channel swap 0 = normal operation 1 = left and right swapped
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 93 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.10. function information (68h page 01h ) register 24h must be set to page 01h to access this register. default: 0010h 2 0 rw das dac-a channel swap 0 = normal operation 1 = left and right swapped 1:0 01 rw hp selen <1:0> headphone select and enable 00b: pins 35/36 = line_out pins 39/41 = line_out 01b: pins 35/36 = headphone_out pins 39/41 = line_out 10b: pins 35/36 = line_out pins 39/41 = headphone_out 11b: reserved (undefined, writing this will set it to 00) d15 d14 d13 d12 d11 d10 d9 d8 g4 g3 g2 g1 g0 inv dl4 dl3 d7 d6 d5 d4 d3 d2 d1 d0 dl2 dl1 dl0 iv reserved fip bit(s) r/w reset value name description 15 rw see table g4 gain sign bit: the codec updates this bit with the sign of the gain value present in g[3:0]. the bios updates this to take into consideration external amplifiers or other external logic when relevant . g [4] indicates whether the value is a gain or attenuation. 14:11 rw see table g3:g0 gain bits: the codec updates these bits with the gain value (db relative to level-out) in 1.5dbv increments. the bios updates these to take into consideration external amplifiers or other external logic when relevant. g[0:3] indicates the magnitude of the gain. g[4] indicates whether the value is a gain or attenuation. f or gain/attenuation settings, see table 21: page94 . t hese bits are read/write and do not reset on reset#. 10 rw see table inv inversion bit: indicates that the codec presents a 180 degree phase shift to the signal. 0 - no inversion reported 1 - inverted t his bit is read/write and do not reset on reset# . b ios should invert for each inverting gain stage. bit(s) reset value r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 94 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 9:5 rw see table dl4:dl0 buffer delays: codec will provide a delay measurement for the input and output channels. software will use this value to accurately calculate audio stream position with respect to what is been reproduced or recorded. these values are in 20.83 microsecond (1/48000 second) units. for output channels, this timing is from the end of ac-link frame in which the sample is provided, until the time the analog signal appears at the output pin. for input streams, this is from when the analog signal is presented at the pin until the representative sample is provided on the ac-link. the measurement is a typical measurement, at a 48khz sample rate, with minimal in-codec processing (i.e., 3d effects are turned off.) 00h - information not provided 01h?1eh - buffer delay in 20.83 m sec units 1fh - reserve d t hese bits are read/write and do not reset on reset# . the default value is the delay internal to the codec. the bios may add to this value the known delays external to the codec, such as for an external amplifier. 4 rw see table iv information valid bit: indicates whether a sensing method is provided by the codec and if information field is valid. this field is updated by the codec. 0h--after codec reset# de-assertion, it indicates the codec does not provides sensing logic and this bit will be read only. after a sense cycle is completed indicates that no information is provided on the sensing method. 1h--after codec reset# de-assertion, it indicates the codec provides sensing logic for this i/o and this bit is read/write. after clearing this bit by writing 1, when a sense cycle is completed the assertion of this bit indicates that there is valid information in the remaining descriptor bits. writing 0 to this bit has no effect. bios should not write this bit, as it is reset on reset#. see table 22: page96 for details on usage of this bit . 3:1 0 0 reserved bit not used, should read back 0 0 ro see table fip function information presen t t his bit set to 1 indicates that the g[4:0], inv, dl[4:0] (register 6ah) are supported and r/w capable . t his bit is read only. table 21. gain or attenuation examples g[4:0] gain or attenuation (db relative to level-out) 00000 0 dbv 00001 1.5 dbv 01111 24 dbv 10001 -1.5 dbv 11111 -24 dbv bit(s) r/w reset value name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 95 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.11. digital audio control (6ah, page 00h ) to access register 6ah, page 00h must be selected in register 24h. default: 0000h this read/write register is used to program the spdif output status. in the default state, the pcm data path from ac_link is enabled and the adc record inputs are disabled. the do1 bit controls the input source for the pcm to digital output converters. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved hpfocdis spor do1 reserved bit(s) reset value r/w name description 15: 0 ro reserved bits not used, should read back 0 3 0 rw hpfocdis high pass filter offset calculation disable 0 = calculation enabled. 1 = calculation disabled. 2 0 rw spor over-ride register 2ah, d12 write-lock when spdif_en = 1. all bits except spdif sample-rate are affected (d13-d12). allows for sub-code changing on-the-fly. 1 0 rw do1 spdif digital output source selection: do1 = 0; pcm data from the ac-link to spdif do1 = 1; adc record data to spdif 0 0 ro reserved bits not used, should read back 0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 96 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.12. sense details (6ah page 01h ) register 24h must be set to page 01h to access this register. default: na d15 d14 d13 d12 d11 d10 d9 d8 st2 st1 st0 s4 s3 s2 s1 s0 d7 d6 d5 d4 d3 d2 d1 d0 or1 or0 sr5 sr4 sr3 sr2 sr1 sr1 bit(s) r/w reset value name description 15-13 rw see table st2:st0 connector/jack location bits this field describes the location of the jack in the system. 0h - rear i/o panel 1h - front panel 2h - motherboard 3h - dock/external 4h:6h - reserved 7h - no connection/unused i/ o t hese bits are read/write. 12-8 ro s4:s0 sensed bits meaning relates to the i/o being sense as output or inputs . s ensed bits (outputs): see table 22: page96. this field allows for the reporting of the type of output peripheral/device plugged in the jack. values specified below should be interrogated in conjunction with the sr[5:0] and or[1:0] bits for accurate reporting . s ensed bits (inputs): see table 22: page96. this field allows for the reporting of the type of input peripheral/device plugged in the jack. values specified below should be interrogated in conjunction with the sr[5:0] and or[1:0] bits for accurate reporting . t his field is read only. 7-6 ro or1:0 order bits. these bits indicate the order the sense result bits sr[5:0] are using. 00 - 10 0 (i.e., ohms) 01 - 10 1 (i.e., 10 ohms) 10 - 10 2 (i.e., 100 ohms) 11 - 10 3 (i.e., 1k ohms) 5-0 ro sr5:sr0 sense result bit s t hese bits are used to report a vendor specific fingerprint or value. (resistance, impedance, reactance, ect). this field is read only. table 22. sensed bits reported value input or output peripheral/device 0h data not valid. indicates that the reported value(s) is (are) invalid. 1h no connection. indicates that there are no connected devices. 2h-9h not used by stac9758/9759 ah indicates that sense results are reported as binary values in s r[5:0] and o r[1:0 ]. bh-eh reserved fh not used by stac9758/9759
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 97 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.13. r evision code (6ch, page 00h ) to access register 6ch, page 00h must be selected in register 24h. default: xxxx h 8.6.14. dac slot mapping (6ch, page 01h ) to access register 6ch, page 01h must be selected in register 24h. default: 3760h d15 d14 d13 d12 d11 d10 d9 d8 minorrev d7 d6 d5 d4 d3 d2 d1 d0 majorrev bit(s) reset value r/w name description 15:12 0 ro reserved bit not used, should read back 0 11:8 ** ro minorrev minor revision id. these bits are read only and will be updated based on minor device changes which will not require software changes. these bits are un-locked with register 70h (d1:d0 = 11) and will read back all 0 when locked. 7:4 0 ro reserved bit not used, should read back 0 3:0 *** ro majorrev major revision id. these bits are read only and will be updated based on major device changes. these bits are not locked. d15 d14 d13 d12 d11 d10 d9 d8 fd3 fd2 fd1 fd0 sd3 sd2 sd1 sd0 d7 d6 d5 d4 d3 d2 d1 d0 cld3 cld2 cld1 cld0 reserved bit(s) reset value r/w name description 15:12 rw fd[3:0] dac-a slot mapping (f ront ) d efault slots 3& 4 11:8 rw sd[3:0] dac-b slot mapping (surround) d efault slots 7&8 7:4 rw cld[3:0] dac- c slot mapping (center/lfe) d efault slots 6&9 3:0 0 ro reserved reserved
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 98 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.15. analog special (6eh, page 00h ) to access register 6eh, page 00h must be selected in register 24h. default: 1000h d15 d14 d13 d12 d11 d10 d9 d8 vrefoutl vl vrefout disable monoout mux ac97mix adc inv dac-a inv dac-b inv dac-cl inv d7 d6 d5 d4 d3 d2 d1 d0 dac-cr inv mutefix disable adcslt1 adcslt0 hp_apop disable mic gain val splyovr en splyovr val bit(s) reset value r/w name description 15 0 rw vrefoutlvl vrefout voltage adjustment when avdd = 5v 0 = vrefout voltage is 0.50 * avdd 1 = vrefout voltage is 0.81 * avdd note: when avdd = 3.3v, vrefout will be 0.46 * avdd regardless of the setting of this bit. the vrefoutdisable bit will override this setting 14 0 rw vrefoutdisable 0 = vrefout voltage available 1 = vrefout voltage not available vrefout goes high z when this bit is set to 1 . 13 0 rw monoout mux mono out has 3 possible sources. register 20:d9 (0 = mixer / 1 = microphone ) if register 20:d9 = 0: *0 = mixer 2 output 1 = dac-a output because of the change in analog architecture and the modification in behavior of reg 20 d15 (pop) this bit is necessary to implement the pop bypass mode dac to mono path. 12 1 rw ac97mix 0 = mixer record contains a mix of all mono and stereo analog input signals, not the dac (all analog mode) 1 = mixer record contains a mix of all mono and stereo analog input signals plus the dac signal ( ac?97 mode ) t his bit only has an effect when either stereo mix or mono mix is selected as the record source in reg 1 ah . t he ? all analog? mode is used t o record all analog sources, perform further processing in the digital domain, including combining with other pcm data, and then route the signal t hrough the dac s directly to the output jacks. a stereo mix recording will be affected by the setting of the 3d effects bit (reg 2 0h , bit d 13) 11 0 rw adc inv 0 = single bit adc data not inverted 1 = single bit adc data is inverted 10 0 rw dac-a inv 0 = single bit dac data 0/ 1 not inverted 1 = single bit dac data 0/ 1 is inverted 9 0 rw dac-b inv 0 = single bit dac data 2 /3 not inverted 1 = single bit dac data 2 /3 is inverted 8 0 rw dac-cl inv 0 = single bit dac data 4 n ot inverted 1 = single bit dac data 4 i s inverted
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 99 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 7 0 rw dac-cr inv 0 = single bit dac data 5 not inverted 1 = single bit dac data 5 is inverted 6 0 rw mutefix disable 0 = mute fix enabled 1 = mute fix disable d w hen mutefix_disable = 0, a volume setting of 1fh on either channel of reg 02h, reg 04h, reg 06h, reg 36h, or reg 38h will cause a mute on that channel. this is independent of the other channel. w hen mutefix_disable = 1, a setting of 1f will cause -46.5db attenuation on the output. with this setting only the mute bit(s) will cause a mute. 5:4 0 rw adcslt1:0 select slots for adc data on aclink 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 1 1 t his bit field is only active when the mv bit (reg 6eh, page 01, bit0) is zero. if the mv bit is set, then this bit field has no effect, and the alternate adc slot mapping registers in reg 6eh, page 01 are used instead. 3 0 rw hp_apop disable 0 = hp apop enabled 1 = hp apop disabled 2 0 rw mic gain val adds +10db gain to the selected mic input. use in conjunction with boosten (reg. 0eh;d6) boosten micgainval 0 0 = 0 db 0 1 = 10 db 1 0 = 20 db 1 1 = 30 db 1 0 rw splyovr_en supply override bit allows override of the supply detect . 0 = no override on supply detect 1 = override supply detect with bit 0 0 0 rw splyovr_val supply override value provides the analog voltage operation values . 0 = force 3.3 v operation 1 = force 5 v operatio n bit(s) reset value r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 100 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.16. adc slot mapping (6eh, page 01h ) to access register 6eh, page 01h must be selected in register 24h. default: 3000h 8.6.17. idt reserved (70h) 8.6.18. various functions (72h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 lia3 lia2 lia1 lia0 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved mv bit(s) reset value r/w name description 15:12 0011 rw lia[3:0] mapping of line in adc, default slots 3&4 11:1 0 ro reserved bit not used, should read back 0 0 0 rw mv mapping valid bit: indicated that the values programmed into page offsets 6ch and 6eh are valid. d15 d14 d13 d12 d11 d10 d9 d8 line_ce mic_ce spl1 spl0 spare alter antipop d7 d6 d5 d4 d3 d2 d1 d0 int apop splitmute sifovrn siper dpll_lock sp_run pr_dac_a stmicen bit(s) reset value r/w name description 15 0 rw line_ce 0 = normal operation 1 = 6db attenuation to allow 2 vrms at input pin for consumer equipment compatibility. 14 0 rw mic_ce 0 = normal operation 1 = 6db attenuation to allow 2 vrms at input pin for consumer equipment compatibility. 13:12 0 rw spl[1:0] loss of dpll lock after 00 = 4 parity errors 01 = 3 parity errors 10 = 2 parity errors 11 = 1 parity errors 11:9 0 rw spare spare 8 0 rw alter antipop 0 = power down to vag 1 = power down to gnd
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 101 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 7 0 rw int_apop 0 = anti pop enabled 1 = anti pop disable d the stac9758/9759 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the codec is powered on and off. this function is accomplished by delaying the charge/discharge of the vref capacitor (pin 27). c vref value of 1 m f will cause a turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the codec outputs are enabled. the delay will be extended to 30 seconds if a value of c vref value of 10 m f is used. the codec outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. the int_apop bit allows this delay circuit to be bypassed for rapid production testing. any external component anti-pop circuit is unaffected by the internal circuit. 6 0 rw splitmute allows separate mute control bits for master, headphone, linein, cd, aux and pcm volume control registers as well as record gain register. 0 = default value: left and right channel mutes are controlled by bit d15 of the respective registers disables writes to all r mute signals and force them to read 0. 1 = bit d15 of respective register affects only the left channel mute and bit d7 affects only the right channel mute enables read and writes to rmute bit in all stereo volume registers. if s plitm ute is not set, the bahav ior is the same as previous codecs . 5 0 rw sifovrn s pdif_in fifo overrun status bit 0 = no overrun occurred (defualt) 1 = overrun has occurre d 4 0 rw siper spdif_in parity error 0 = no parity error occurred (defualt) 1 = parity error occurred 3 0 ro dpll_lock digital pll lock 0 = dpll not locked 1 = dpll locked to spdif _in and data valid 2 0 ro sp_run spdif running 0 = no signal on pin 47 1 = signal on pin 47 1 0 rw pr_dac_a powerdown bit for first dac 1 = powerdown 0 = normal operation this is equivalent to pri, prj, and prk, but applies to the first dac which is not otherwise accomodated 0 0 rw stmicen stereo mic enable 0 = mono 1 = stereo if this bit is 1, then reg 20h, d8, causes left/right swap when set to 1. bit(s) reset value r/w name description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 102 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.19. eapd access register (74h) default: 0800h d15 d14 d13 d12 d11 d10 d9 d8 eapd reserved eapd_oen reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved intdis gpioacc gpioslt12 bit(s) reset value r/w name description 15 0 rw eapd eapd da ta eapd data output on eapd when bit d11 = 1 eapd data input from pin when bit d11 = 0 14:12 0 ro reserved bit not used, should read back 0 11 1 rw eapd_oen eapd pin ouput enable 0 = eapd configured as input pin 1 = eapd configured as output pin 10:3 0 ro reserved bit not used, should read back 0 2 0 rw intdis interrupt disable option. interrupts cleared by writing a 1 to i4 (reg24h:d15 ) 0 = will clear both sense and gpio interrupts 1 = will only clear sense interrupts. gpio interrupts will have to be cleared in reg54h. 1 0 rw gpioacc gpio access - gpios configured as input pass their state to ac link in 1 of two ways: 0 = gpio pin connects directly to ac link 1 = ac link value reflects register 54h (sticky, invert, etc applied ) this can only be used if a modem codec is not present in the system and using slot 12. 0 0 rw gpioslt12 for inputs: 0 = input state only read from register 54h. ac link slot 12 returns 0. 1 = input state reflected on ac_link slot 12. for outputs: 0 = gpio[3:0] pad state is controlled via reg54h. 1 = gpio[3:0] pad state is controlled by ac link slot 12. register 54h is not updated . t his can only be used if a modem codec is not present in the system and using slot 12.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 103 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.6.20. analog misc. (76h) default: 0000h 8.6.21. adat control and hpf bypass (78h) default: 0000h 8.6.22. idt reserved register (7ah) d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved js_manual js_stereo disable d15 d14 d13 d12 d11 d10 d9 d8 adat3 adat2 adat1 adat0 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved dac sync adc hpf byp bit(s) reset value r/w name description 15:12 0000 rw adat <3:0> adat lightpipe control 11:2 0 ro reserved bits not used, should read back 0 1 0 rw dac sync synchronize dacs to channel 0 when at same sample rate 0 = enabled 1 = disables dac sync 0 0 rw adc hpf byp 0 = normal operation, (adc high pass filter active) 1 = adc high pass filter bypass
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 104 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 8.7. vendor id1 and id2 (7ch and 7eh) these two registers contain four 8-bit id codes. the first three codes have been assigned by microsoft using their plug and play vendor id methodology. the fourth code is an idt assigned code identifying the stac9758/9759 . the id1 register (index 7ch) contains the value 8384h, which is the first (83h) and second (84h) bytes of the microsoft id code. the id2 register (index 7eh) con- tains the value 7658h, which is the third (76h) byte of the microsoft id code, and 58h which is the stac9758/9759 id code. 8.7.1. vendor id1 (7ch) default: 8384h 8.7.2. vendor id2 (7eh) default: 7658h d15 d14 d13 d12 d11 d10 d9 d8 1 0 0 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 1 0 0 d15 d14 d13 d12 d11 d10 d9 d8 0 1 1 1 0 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 0 0 0
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 105 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 9. low power modes the stac9758/9759 i s capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). there are 7 commands of sep- arate power down. the power down options are listed in table 23. the first three bits, pr0..pr2, can be used individually or in combination with each other, and control power distribution to the adcs, dacs and mixer. the last analog power control bit, pr3, affects analog bias and reference voltages, and can only be used in combination with pr1, pr2, and pr3. pr3 essentially removes power from all analog sections of the codec and is generally only asserted when the codec will not be needed for long periods. pr0 and pr1 control the pcm adcs and dacs only. pr2 and pr3 do not need to be set before a pr4, but pr0 and pr1 should be set before pr4. pr5 disables the dsp clock and does not require an external cold reset for recovery. if pr0 and pr1 are set together, it is the same as setting pr5. pr6 disables the headphone driver amplifier for additional analog power saving. figure 20. example of stac9758/9759 powerdown/powerup flow the figure 20 illustrates one example procedure to do a complete powerdown of stac9758/9759 . from normal operation, sequential writes to the powerdown register are performed to power down stac9758/9759 a section at a time. after everything has been shut off, a final write (of pr4) can be executed to shut down the ac-link. the part will remain in sleep mode with all its registers holding their static values. to wake up, the ac'97 controller will send an extended pulse on the sync line, issuing a warm reset. this will restart the ac-link (resetting pr4 to zero). the stac9758/9759 c an also be woken up with a cold reset. a cold reset will reset all of the registers to their default states (paged registers are semi-exempt). when a section is powered back on, the powerdown control/ status register (index 26h) should be read to verify that the section is ready (stable) before attempt- ing any operation that requires it. table 23. low power modes grp bits function pr0 pcm in adcs & input mux powerdown pr1 pcm out dacs powerdown pr2 analog mixer powerdown (vref still on) pr3 analog mixer powerdown (vref off) pr4 digital interface (ac-link) powerdown (bit clk forced low) pr5 digital clk disable, bit clk still on pr6 powerdown headphone_out warm reset cold reset ready =1 normal adcs off pr0 dacs off pr1 analog off pr2 or pr3 digital i/f off pr4 shut off ac-link default pr0=0 & adc=1 pr1=0 & dac=1 pr2=0 & anl=1 pr0=1 pr1=1 pr2=1 pr4=1
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 106 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? figure 21. powerdown/powerup flow with analog still active figure 21 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. this configuration can be used when playing a cd (or exter- nal line_in source) through stac9758/9759 t o the speakers, while most of the system in low power mode. the procedure for this follows the previous except that the analog mixer is never shut down. warm reset normal adcs off pr0 dacs off pr1 digital i/f off pr4 shut off ac-link pr0=0 & adc=1 pr1=0 & dac=1 pr0=1 pr1=1 pr4=1
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 107 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 10. multiple codec support the stac9758/9759 p rovides support for the multi-codec option according to the intel ac'97, rev 2 .3 specification. th e codec id functions as a chip select. secondary devices therefore have com- pletely orthogonal register sets; each is individually accessible and they do not share registers. the stac9758/9759 supports only the codec id 10 in secondary mode (ids 01 and 11 are not sup- ported). 10.1. primary/secondary codec selection in a multi-codec environment the codec id is provided by external programming of pin46 (cid1). the cid pin electrical function is logically inverted from the codec id designation. the cor- responding pin state and its associated codec id are listed in the "codec id selection" table. also see slot assignment discussion, ?multi-channel programming register (index 74)?. 10.1.1. primary codec operation as a primary device the stac9758/9759 i s completely compatible with existing ac'97 definitions and extensions. primary codec registers are accessed exactly as defined in the ac'97 component specification and ac'97 extensions. the stac9758/9759 operates as primary by default, and the external id pin (46), has an internal pull-up so that this pin may be left as no-connect for primary operation. when used as the primary codec, the stac9758/9759 g enerates the master ac-link bit_clk for both the ac'97 digital controller and any secondary codecs. the stac9758/9759 c an support up to four, 10k w /50pf loads on the bit_clk output. this is to ensure that up to four codec implementations will not load down the clock output. 10.1.2. secondary codec operation when the stac9758/9759 i s configured as a secondary device the bit_clk pin is configured as an input at power up. using the bit_clk provided by the primary codec insures that everything on the ac-link will be synchronous. as a secondary device it can be defined as codec id 10 in the two-bit field(s) of the extended audio and/or extended modem id register(s). the stac9758/9759 supports only the codec id 10 in secondary mode (ids 01 and 11 are not supported). table 24. codec id selection xtal out pin state cid1 pin state cid0 pin state codec id codec status gnd dvdd or floating na 00 primary xtl / float 0v na 10 secondary
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 108 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 10.2. secondary codec register access definitions the ac'97 digital controller can independently access primary and secondary codec registers by using a 2-bit codec id field (chip select) which is defined as the lsbs of output slot 0. for sec- ondary codec access, the ac'97 digital controller must invalidate the tag bits for slot 1 and 2 command address and data (slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the codec id field (slot 0, bits 1 and 0). as a secondary codec, the stac9758/9759 w ill disregard the command address and command data (slot 0, bits 14 and 13) tag bits when it sees a 2-bit codec id value (slot 0, bits 1 and 0) that matches its configuration. in a sense the secondary codec id field functions as an alternative valid command address (for secondary reads and writes) and command data (for secondary writes) tag indicator. secondary codecs must monitor the frame valid bit, and ignore the frame (regardless of the state of the secondary codec id bits) if it is not valid. ac'97 digital controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the secondary codec id bits are set. this method is designed to be backward compatible with existing ac'97 controllers and codecs. there is no change to output slot 1 or 2 definitions. using three codecs typically requires a controller to support sdata_in2. table 25. secondary codec register access slot 0 bit definitions output tag slot (16-bits) bit description 15 frame valid 14 slot 1 valid command address bit (?primary codec only) 13 slot 2 valid command data bit (?primary codec only) 12-3 slot 3-12 valid bits as defined by ac'97 2 reserved (set to 0) ?1-0 2-bit codec id field (00 reserved for primary; 01, 10, 11 indicate secondary) note: ? new definitions for secondary codec register access
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 109 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 11. testability the stac9758/9759 h as three test modes. one is for ate in-circuit test and the other two are restricted for internal use. stac9758/9759 e nters the ate in-circuit test mode if sdata_out is sampled high at the trailing edge of reset#. once in the ate test mode, the digital ac-link outputs (bit_clk and sdata_in) are driven to a high impedance state. this allows ate in-circuit testing of the ac'97 controller. use of the ate test mode is the recommended means of removing the codec from the ac-link when another codec is to be used as the primary. this case will never occur dur- ing standard operating conditions. once either of the two test modes have been entered, the stac9758/9759 m ust be issued another reset# with all ac-link signals held low to return to the normal operating mode. 11.1. ate test mode ate test mode allows for in-circuit testing to be completed at board level. for this to work, the out- puts of the device must be driven to a high impedance state (z). internal pull-ups and pull-downs for i/o pins are also disabled in this mode. this is the lowest power mode for the device. this mode ini- tiates on the rising edge of reset# pin. only a cold reset will exit the ate test mode. table 26. test mode activation sync sdata_out description 0 0 normal ac'97 operation 0 1 ate test mode 1 0 internal test mode s 1 1 reserved table 27. ate test mode operation pin name pin # function description sdata_out 5 1 must be held high at the rising edge of reset# bit_clk 6 z h igh impedance state sdata_in 8 z high impedance state sync 10 0 must be held low at rising edge of reset# reset# 11 1 high impedance state gpio0 31 z high impedance state gpio1 33 z high impedance state gpio2 34 z high impedance state gpio3 45 z high impedance state cid1 46 z high impedance state eapd/spdifi 47 z high impedance state spdifo/adat 48 z high impedance state
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 110 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 12. p in description 12.1. digital i/o these signals connect the stac9758/9759 to its ac'97 controller counterpart, an external crystal, multi-codec selection and external audio amplifier. table 28. digital connection signals pin name pin # typ e description xtl_in 2 i 24.576 mhz crystal or external clock source d v d d 1 1 x t l _ i n 2 x t l _ o u t 3 d v s s 1 4 s d a t a _ o u t 5 b i t _ c l k 6 d v s s 2 7 s d a t a _ i n 8 d v d d 2 9 s y n c 1 0 r e s e t # 1 1 p c _ b e e p 1 2 24 line_in_r* 23 line_in_l* 22 mic1_r* 21 mic1_l* 20 cd_r 19 cd_gnd 18 cd_l 17 mic2_r 16 mic2_l 15 aux_r 14 aux_l 13 phone mono 37 avdd2 38 surr_l* 39 avss3 40 surr_r* 41 avss2 42 ctr* 43 lfe* 44 gpio3 45 cid1 46 eapd/spdifi 47 spdifo/adat 48 figure 22. pin description drawin g note: for use of pins 16/17 for video, see section 8.2.11.1: page60. note: if pin 48 is held high at powerup, register 28h (extended audio id), bit[2] will be held to zero, to indicate the spdif is not available. tie pin 48 to ground with a 10 k w resistor to ensure spdif is enabled. 48-pin tqfp 3 6 f r o n t _ r * 3 5 f r o n t _ l * 3 4 g p i o 2 3 3 g p i o 1 3 2 c a p 2 3 1 g p i o 0 3 0 a f i l t 2 2 9 a f i l t 1 2 8 v r e f o u t 2 7 v r e f 2 6 a v s s 1 2 5 a v d d 1
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 111 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 12.2. analog i/o these signals connect the stac9758/9759 to analog sources and sinks, including microphones and speakers. xtl_out 3 i/o 24.576 mhz crystal sdata_out 5 i serial, time division multiplexed, ac'97 input stream bit_clk 6 i/o 12.288 mhz serial data clock sdata_in 8 o serial, time division multiplexed, ac'97 output stream sync 10 i 48 khz fixed rate sample sync reset# 11 i ac'97 master h/w reset gpio0 31 i gpio tied to avdd . gpio 1 33 i/o gpio tied to avdd. gpio 2 34 i/o gpio tied to avdd gpio 3 45 i/o gpio tied to dvdd cid1 46 i clock input frequency select or multi- codec id select. eapd/spdifi 47 i/o external amplifier power down (gpio) /spdif_i n spdifo/ adat 48 o sp dif digital output or adat lightpipe output note: if pin 48 is held high at powerup, register 28h (extended audio id) bit [2] will be held to zero, to indicate the spdif is not available. tie pin 48 to ground with a 10k w resistor to ensure spdif is enabled. table 29. analog connection signals pin name pin # type description pc-beep 12 i** pc speaker beep pass-through phone 13 i** from telephony subsystem speakerphone aux_l 14 i** aux left channel aux_r 15 i** aux right channel mic2_l* 16 i** front panel mic l eft channel mic2_r* 17 i** front panel mic right c hannel cd_l 18 i** cd audio left channel cd_gnd 19 i** cd audio analog ground cd_r 20 i** cd audio right channel mic1_l* 21 i/o* desktop microphone input mic1_r* 22 i/o* second microphone input line_in_l* 23 i/o* line in left channel line_in_r* 24 i/o* line in right channel front_l* 35 i/o* line out left channel (with headphone support) table 28. digital connection signals pin name pin # typ e description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 112 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 1. ** any unused input pins should be tied together and tied to ground through a capacitor (0.1 f suggested), except the mic inputs, which should have a separate capacitor to ground if not used. 2. * universal jack ? capable. these pins may be inputs or outputs and are controlled by registers 64 and 66 (page 0). only pins 35/36 or 39/41 may be used to drive headphones. it is not possible to drive 2 sets of headphones at the same time. 3. for use of pins 16/17 for video, see section 8.2.11.1: page60 . 12.3. filter/references these signals are connected to resistors, capacitors, or specific voltages. 12.4. power and ground signals front_r* 36 i/o* line out right channel (with headphone support) mono 37 o to telephony subsystem speakerphone surr_l* 39 i/o* surround o ut left channel (with headphone support) avss3 40 i headphone ground return surr_r* 41 i/o* surround o ut right channel (with headphone support) ctr* 43 i/o* center output lfe* 44 i/o* lfe output table 30. filtering and voltage references signal name pin number type description vref 27 o analog ground (.45*vdd, at 5v;.41*vdd at 3v) vrefout 28 o reference voltage out 5ma drive (intended for mic bias) (~vdd/2) afilt1 29 o anti-aliasing filter cap - adc left channel afilt2 30 o anti-aliasing filter cap - adc right channel cap2 32 o adc reference cap table 31. power and ground signals pin name pin # type description avdd1 25 i analog vdd = 5.0 v or 3.3 v avdd2 38 i analog vdd = 5.0 v or 3.3 v avss1 26 i analog gnd avss2 42 i analog gnd avss3 40 i analog gnd dvdd1 1 i digital vdd = 3.3 v dvdd2 9 i digital vdd = 3.3 v dvss1 4 i digital gnd dvss2 7 i digital gnd table 29. analog connection signals pin name pin # type description
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 113 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 13. ordering information note: yy is the revision, contact sales for current orderables. add an ?r? to the end of any of these part numbers for delivery on tape and reel. the minimum order quantity for tape and reel is 2,000 units for both package options. 14. package drawing part number package temp range supply range STAC9758XXTAEYYX 48-pin tqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3 v, avdd = 5.0 v stac9759xxtaeyyx 48-pin tqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3 v, avdd = 3.3 v key lqfp dimensions in mm min. nom. max. a 1.40 1.50 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 d 8.80 9.00 9.20 d1 6.90 7.00 7.10 e 8.80 9.00 9.20 e1 6.90 7.00 7.10 l 0.45 0.60 0.75 e 0.50 c 0.09 - 0.20 b 0.17 0.22 0.27 48 pin lqfp e e 1 d d 1 pin 1 b a a 2 a 1 c e
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 114 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 15. solder reflow profile 15.1. standard reflow profile data note: these devices can be hand soldered at 360 o c for 3 to 5 seconds. from: ipc / jedec j-std-020c ?moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices? (www.jedec.org/download). figure 23. solder reflow profile profile feature pb free assembly average ramp-up rate (ts max - tp) 3 o c / second max preheat temperature min (ts min ) temperature max (ts max ) time (ts min - ts max ) 150 o c 200 o c 60 - 180 seconds time maintained above temperature (t l ) time (t l ) 217 o c 60 - 150 seconds peak / classification temperature (tp) see ? package classification reflow temperatures? on page 115 . time within 5 o c of actual peak temperature (tp) 20 - 40 seconds ramp-down rate 6 o c / second max time 25 o c to peak temperature 8 minutes max note: all temperatures refer to topside of the package, measured on the package body surface.
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 115 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 15.2. pb free process - package classification reflow temperatures package type msl reflow temperature tqfp 48-pin 3 260 o c*
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 116 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 16. appendix a: programming registers reg # name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset rsrvd se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 6a90h 02h master volume mute rsvd ml5 ml4 ml3 ml2 ml1 ml0 rmute rsvd mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h dac-a volume mute rsvd hpl5 hpl4 hpl3 hpl2 hpl1 hpl0 rmute rsvd hpr5 hpr4 hpr3 hpr2 hpr1 hpr0 8000h 06h master volume mono mute reserved mm5 mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute rsvd pc_ beep_fd f7 f6 f5 f f3 f2 f1 f0 pv3 pv2 pv1 pv0 rsrvd 0000h 0ch phone volume mute reserved gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mono allmute reserved gnl4 gnl3 gnl2 gnl1 gnl0 rmute boost en rsrvd gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume stereo lmute reserved gnl4 gnl3 gnl2 gnl1 gnl0 rmute boost en rsrvd gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute reserved gl4 gl3 gl2 gl1 gl0 rmute reserved gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute reserved gl4 gl3 gl2 gl1 gl0 rmute reserved gr4 gr3 gr2 gr1 gr0 8808h 14h dac-b to mixer2 volume mute reserved gl4 gl3 gl2 gl1 gl0 rmute reserved gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute reserved gl4 gl3 gl2 gl1 gl0 rmute reserved gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute reserved gl4 gl3 gl2 gl1 gl0 rmute reserved gr4 gr3 gr2 gr1 gr0 8808h 1ah record select reserved sl2 sl1 sl0 reserved sr2 sr1 sr0 0000h 1ch record gain mute reserved gl3 gl2 gl1 gl0 rmute reserved gr3 gr2 gr1 gr0 8000h 20h general purpose pop rsrvd 3d rsvd drss1 drss0 mix ms lpbk reserved 0000h 22h 3d control reserved dp3 dp2 reserved 0000h 24h audio int. & paging i4 i3 i2 i1 i0 reserved pg3 pg2 pg1 pg0 0000h 26h powerdown ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 reserved ref anl dac adc 000fh 28h extended audio id id1 id0 reserved rev1 rev0 amap ldac sdac cdac dsa1 dsa0 rsvd spdif dra vra 0bc7 2ah extended audio control/status vcfg prl prk prj pri spcv madc ldac sdac cdac spsa1 spsa0 vrm/ rsvd spdif dra vra 05f0h 2ch pcm dac rate (dac a & dac-cl sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 2eh pcm surr dac rate (dac-b) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 30h pcm lfe dac rate (dac-cr) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm lr adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 36h center/lfe volume mute rsvd lfe5 lfe4 lfe3 lfe2 lfe1 lfe0 mute rsvd cnt5 cnt4 cnt3 cnt2 cnt1 cn0 8080h 38h surround volume mute rsvd lsr5 lsr4 lsr3 lsr2 lsr1 lsr0 mute rsvd rsr5 rsr4 rsr3 rsr2 rsr1 rsr0 8080h 3ah spdif control #v drs spsr1 spsr2 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy #pcm/ audio pro 2000h 3eh extended modem status reserved pra reserved gpio 0100h 4ch gpio pin config reserved gc3 (gpio3) gc2 (gpio2) gc1 (gpio1) gc0 (gpio0) 000fh 4eh gpio pin polarity/type reserved gp3 (gpio3) gp2 (gpio2) gp1 (gpio1) gp0 (gpio0) ffffh 50h gpio pin sticky reserved gs3 (gpio3) gs2 (gpio2) gs1 (gpio1) gs0 (gpio0) 0000h 52h gpio pin mask reserved gw3 (gpio3) gw2 (gpio2) gw1 (gpio1) gw0 (gpio0) 0000h 54h gpio pin status reserved gi3 (gpio3) gi2 (gpio2) gi1 (gpio1) gi0 (gpio0) 0000h 60h page 00h spdif_in status1 lvl cc6 cc5 cc4 cc3 cc2 cc1 cc0 mode1 mode0 pre2 pre1 pre0 cpy /aud pro 0000h 60h page 01h codec class/rev x x x cl4 cl3 cl2 cl1 cl0 rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 18xxh 62h page 00h spdif_in status2 sp_val rsvd ca1 ca0 fs3 fs2 fs1 fs0 cn3 cn2 cn1 cn0 sn3 sn2 sn1 sn0 0000h 62h page 01h pci svid pvi15 pvi14 pvi13 pvi12 pvi11 pvi10 pvi9 pvi8 pvi7 pvi6 pvi5 pvi4 pvi3 pvi2 pvi1 pvi0 ffffh 64h page 00h universal jacks tm output select csen cs1 cs0 rsen rs1 rs0 fsen fs1 fs0 ls2 ls1 ls0 msen ms1 ms0 rsvd d794h 64h page 01h pci sid pi15 pi14 pi13 pi12 pi11 pi10 pi9 pi8 pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 ffffh 66h page 00h universal jacks tm input select reserved li2 li1 li0 reserved mi2 mi1 mi0 0201h 66h page 01h function select reserved fc3 fc2 fc1 fc0 t/r 0000h
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 117 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 68h page 00h i/o misc noblk chk spisa1 spisa0 spi_se len1 spi_se len0 vi amute hp3db p48mo p47m1 p47m0 dcs dbs das hp_sel en1 hp_sel en0 2001h 68h page 01h function information g4 g3 g2 g1 g0 inv dl4 dl3 dl2 dl1 dl0 iv reserved fip 0010h 6ah page 00h digital audio control reserved hpfoc dis spor do1 rsvd 0000h 6ah page 01h sense details st2 st1 st0 s4 s3 s2 s1 s0 or1 or0 sr5 sr4 sr3 sr2 sr1 sr0 na 6ch revision code xxxxh 6ch page 01h dac slot mapping fd3 fd2 fd1 fd0 sd3 sd2 sd1 sd0 cld3 cld2 cld1 cld0 reserved 3760h 6eh analog special vrefo utlvl vrefo utdis able mono out mux ac?97 all mix acd inv dac-a inv dac-b inv dac-cl inv dac- cr inv mute fix disble adc slot1 adc slot0 hp_ apop disble mic gain value sply ovr en sply ovr val 1000h 6eh page 01h adc slot mapping lia3 lia2 lia1 lia0 ima3 ima2 ima1 ima0 reserved mv 3000h 70h idt reserved reserved 72h various functions line_c e mic_c e spl1 spl0 rsvd alter antipop int apop split mute sif ovrn siper dpll_ lock sp_ run pr_ dac_a stmic en 0000h 74h eapd access eapd reserved eapd_ oen reserved intdis gpio acc gpio slt12 0800h 76h analog misc. reserved js_ma nual js-ste reo disble 0000h 78h adat and hpf bypass adat3 adat2 adat1 adat0 reserved dac sync adc hpf byp 0000h 7ah idt reserved reserved 7ch vendor id1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 8384h 7eh vendor id2 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0 0 7658h reg # name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default
stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio idt? 118 stac9758/9759 v 1.2 1206 high-performance 6-channel ac?97 2.3 codec with universal jacks? 17. revision history revision date description of change 1.0 updated power consumption numbers. inserted performance numbers to replace tbds. corrected register 68, page 0, bit d8 (hp3db) inverted values. corrected register 68, page 0, bit d6:5 values. corrected error in the stereo mic register and spdif receiver referenced in mixer diagram. removed use of bit_clk as an input, incorrectly included in the 0.9 release. corrected secondary mode usage models. included video input usage model section and relevant references. placed spdif out pin note on connection diagram and pin out. corrected misc. grammar, doc flow and typographical errors. removed preliminary status. 1.1 16 october 2006 release in idt format. 1.2 dec 2006 corrected orderable information
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names an d marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support ha.cm@idt.com innovate with idt audio for high fidelity . contact: www.idt.com stac9758/9759 high-performance 6-channel ac?97 2.3 codec with universal jacks? pc audio

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